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ADIN1300CCPZ-R7 Scheda tecnica(PDF) 77 Page - Analog Devices |
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ADIN1300CCPZ-R7 Scheda tecnica(HTML) 77 Page - Analog Devices |
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77 / 96 page ![]() Data Sheet ADIN1300 REGISTER SUMMARY analog.com Rev. B | 77 of 96 This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator. Table 93. Bit Descriptions for FG_IFG_LEN Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R [7:0] FG_IFG_LEN Interframe gap length in bytes. 0xC R/W Frame Generator Number of Frames High Register Address: 0x941C, Reset: 0x0000, Name: FG_NFRM_H This register is Bits[31:16] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled or restarted. Table 94. Bit Descriptions for FG_NFRM_H Bits Bit Name Description Reset Access [15:0] FG_NFRM_H Bits[31:16] of the Number of Frames to be Generated. 0x0 R/W Frame Generator Number of Frames Low Register Address: 0x941D, Reset: 0x0100, Name: FG_NFRM_L This register is Bits[15:0] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled or restarted. Table 95. Bit Descriptions for FG_NFRM_L Bits Bit Name Description Reset Access [15:0] FG_NFRM_L Bits[15:0] of the Number of Frames to be Generated. 0x100 R/W Frame Generator Done Register Address: 0x941E, Reset: 0x0000, Name: FG_DONE This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H register and FG_NFRM_L register (Address 0x941C and Address 0x941D, respectively). Table 96. Bit Descriptions for FG_DONE Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FG_DONE This bit reads as 1'b1 to indicate that the generation of frames has completed. When set, this bit goes high and it latches high until it is unlatched by reading. 0x0 R FIFO_SYNC Register Address: 0x9427, Reset: 0x0000, Name: FIFO_SYNC When set, the transmit FIFO is configured for synchronous operation (except in 1000BASE-T slave mode) to minimize latency. Table 97. Bit Descriptions for FIFO_SYNC Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R |
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