ADIN1300CCPZ-R7 datasheet(63/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 63 of 96

Table 55. Bit Descriptions for IRQ_STATUS (Continued)

Bits

Bit Name

Description

Reset

Access

FC_FG_IRQ_STAT

If the frame checker/generator interrupt status bit is 1, this indicates that the associated interrupt

triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by

reading.

0x0

R LH

PAGE_RX_IRQ_STAT

If the autonegotiation page received interrupt status bit is 1, this indicates that the associated

interrupt triggered since last read. Note that when this bit goes high, it latches high until it is

unlatched by reading.

0x0

R LH

IDLE_ERR_CNT_IRQ_STAT

If the idle error counter saturated interrupt status bit is 1, this indicates that the associated

interrupt triggered since last read. Note that when this bit goes high, it latches high until it is

unlatched by reading.

0x0

R LH

FIFO_OU_IRQ_STAT

If the MAC interface RGMII transmit FIFO overflow/underflow interrupt status bit is 1, this

indicates that the associated interrupt triggered since last read. Note that when this bit goes high,

it latches high until it is unlatched by reading.

0x0

R LH

RX_STAT_CHNG_IRQ_STAT

If the receive status changed interrupt status bit is 1, this indicates that the associated interrupt

triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by

reading.

0x0

R LH

LNK_STAT_CHNG_IRQ_STAT

If the link status changed interrupt status bit is 1, this indicates that the associated interrupt

triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by

reading.

0x0

R LH

SPEED_CHNG_IRQ_STAT

If the speed changed interrupt status bit is 1, this indicates that the associated interrupt triggered

since last read. Note that when this bit goes high, it latches high until it is unlatched by reading.

0x0

R LH

IRQ_PENDING

If the interrupt pending status bit is 1, this indicates that an interrupt has occurred and is pending.

Note that when this bit goes high, it latches high until it is unlatched by reading.

0x0

R LH

PHY Status 1 Register

Address: 0x001A, Reset: 0x0300, Name: PHY_STATUS_1

This register provides access to various PHY status registers.

Table 56. Bit Descriptions for PHY_STATUS_1

Bits

Bit Name

Description

Reset

Access

PHY_IN_STNDBY

A 1 indicates that the PHY is in standby state and does not attempt to bring up links. The standby state can

be used to run diagnostics, including cable diagnostics.

0x0

MSTR_SLV_FLT_STAT

Master Slave Configuration Fault Status Bit. A 1 indicates that a fault has occurred in the resolution of

master/slave. This bit is a copy of MSTR_SLV_FLT, (MSTR_SLAV_STATUS register, Address 0x000A).

Reading the MSTR_SL_FLT_STAT bit does not clear MSTR_SLV_FLT.

0x0

PAR_DET_FLT_STAT

Parallel Detection Fault Status Bit. A 1 indicates that a fault has occurred in the parallel detection

process. This bit is a copy of PAR_DET_FLT, (AUTONEG_EXP register, Address 0x0006). Reading the

PAR_DET_FLT_STAT bit does not clear PAR_DET_FLT.

0x0

AUTONEG_STAT

Autonegotiation Status Bit. A 1 indicates that autonegotiation has completed. This bit is a copy of AUTO-

NEG_DONE (MII_STATUS register, Address 0x0001). Reading the AUTONEG_STAT bit does not clear

AUTONEG_DONE.

0x0

PAIR_01_SWAP

A 1 indicates that Pair 0 and Pair 1 have been swapped.

0x0

B_10_POL_INV

A 1 indicates that the polarity of the 10BASE-T signal has been inverted.

0x0

[9:7]

HCD_TECH

This field indicates the resolved technology after the link is established.

0x6

111: reserved.

110: reserved.

101: speed resolved to 1000BASE-T full duplex.

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