ADIN1300CCPZ-R7 datasheet(11/96 Pages) AD

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Data Sheet

ADIN1300

SPECIFICATIONS

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Rev. B | 11 of 96

Table 8. MII 10BASE-Te Receive Timing (See Figure 6) (Continued)

Parameter

Description

Min

Typ

Max

Unit

RX_CLK low time

140

200

260

RX_CLK rise/fall time

MII output signal (RXD_0 to RXD_3, RX_DV, RX_ER) setup time to RX_CLK

MII output signal (RXD_0 to RXD_3, RX_DV, RX_ER) hold time to RX_CLK

RGMII Transmit/Receive

Table 9. RGMII Timing

Parameter1, 2

Description

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)3

−500

+500

Data to clock input skew (at receiver)3

1.8

2.6

Data to clock output setup time (at transmitter – internal delay)4

1.2

2.0

Clock to data output hold time (at transmitter – internal delay)4

1.2

2.0

Data to clock input setup time (at receiver – internal delay)4

1.0

2.0

Clock to data input hold time (at receiver – internal delay)4

1.0

2.0

tCYC

Clock cycle duration5

7.2

8.8

Duty_G

Duty cycle for Gigabit

Duty_T

Duty cycle for 10/100 Mbps

tR/tF

Rise/fall time (20% to 80%)

0.75

1 Timing specifications as per RGMII v2.0 standard.

2 Refer to example diagrams in the RGMII Timing Examples section.

3 When operating without RGMII internal delay, the printed circuit board (PCB) design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns

and less than 2.0 ns is added to the associated clock signal. For 10/100 Mbps, the max value is unspecified.

4 Hardware and software programmable internal delay may be enabled or disabled.

5 For 10 Mbps and 100 Mbps, tCYC scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

Figure 7. RGMII Transmit Timing

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