ADIN1300CCPZ-R7 datasheet(39/96 Pages) AD

39 / 96 page

Data Sheet

ADIN1300

TYPICAL POWER CONSUMPTION

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Rev. B | 39 of 96

Table 1 and the Typical Performance Characteristics section cap-

ture high level detail of the power consumption of the ADIN1300

under nominal conditions and across the device temperature range.

Power consumption of a PHY depends heavily on power supply,

speed established, operating condition, and capacitive loading on

digital pins.

POWER SUPPLIES

The most significant contributor to power consumption is the supply

voltage choice and speed of operation.

The ADIN1300 can operate from a minimum of two power supply

rails, where AVDD_3P3 = VDDIO = 3.3 V and DVDD_0P9 = 0.9

V. The VDDIO voltage requirements are dictated by the MAC

interface. While two power supply rails result in a more simplified

power strategy, the higher digital supply voltage translates directly

to higher power consumption needs. This can be seen in Table

28, Table 29, and Table 30, which describe the various VDDIO

voltages. Using the lowest VDDIO supply rail can achieve a savings

close to 100 mW at Gigabit speeds with full throughput.

Speed of Link Established

The next biggest contributor to power consumption is the speed of

the link. The ADIN1300 PHY has leading edge power consumption

figures for Gigabit data. Lower data links run at lower power

consumption numbers. This PHY was designed for low power con-

sumption when operating at Gigabit speeds. As a result, 10 Mbps

power consumption may not be as low as comparable offerings in

the industry.

Lower Power Modes

The ADIN1300 has a number of means to lower power consump-

tion under conditions where the PHY is not active or when it is

linked and there is no data transmitting. Full details on these modes

are captured in the Power-Down Modes section. Two key modes of

operation to minimize power are energy detect power-down mode,

when no link is present, and EEE low power idle mode, where a

link is established but the line is idle. The power consumption under

this state is significantly reduced compared to other idle states.

Configuration of these modes is available through the hardware

configuration pins or directly through the MDI interface. Typical

power consumption for hardware reset, EEE, and EDPD are cap-

tured in Table 28, Table 29, and Table 30 as EEE.

Data Utilization

Table 28, Table 29, and Table 30 also capture the variation for data

utilization for the various speeds. Data is shown for 100% data to

0% or idle state. In the idle state, the PHY is linked, but no data

transfer is taking place. The power consumption in this state is

lower than full utilization.

Table 28. Typical Current and Power Consumption for VDDIO = 1.8 V (TA = 25°C, Cable Length = 100 meters)

Mode

DVDD_0P9 Core Supply, 0.9 V

(mA)

VDDIO Digital I/O Supply, 1.8 V

(mA)

AVDD_3P3 PHY AFE, LED Circuit, 3.3 V

(mA)

Total Power (mW)

Gb, 100% Data

70.5

330

Gb, Idle

70.5

317

100 Mbps, 100% Data

140

100 Mbps, Idle

138

10 Mbps, 100% Data

158

10 Mbps, Idle

117

Software Power-Down

Cable Unplug

Hardware Power-Down

Table 29. Typical Current and Power Consumption for VDDIO = 2.5 V (TA = 25℃, cable length = 100 meters)

Mode

DVDD_0P9 Core Supply, 0.9 V

(mA)

VDDIO Digital I/O Supply, 2.5 V

(mA)

AVDD_3P3 PHY AFE, LED Circuit, 3.3 V

(mA)

Total Power (mW)

Gb, 100% Data

70.5

370

Gb, Idle

70.5

342

100 Mbps, 100% Data

148

100 Mbps, Idle

145

10 Mbps, 100% Data

165

10 Mbps, Idle

123

Software Power-Down

Cable Unplug

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