ADIN1300CCPZ-R7 datasheet(8/96 Pages) AD

8 / 96 page

Data Sheet

ADIN1300

SPECIFICATIONS

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Rev. B | 8 of 96

Table 1. (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Clock Input Frequency (CLK_IN)

MHz

Requirements for external clock applied to XTAL_I pin, MII,

RGMII modes

MHz

RMII mode

Clock Input Voltage Range (CLK_IN)

1.62

3.63

1 MAC interface capacitive load of 5 pF, REFCLK is disabled.

2 The DPTH_MII_BYTE register defines whether the programmed transmit first in, first out (FIFO) depth is bytes or nibbles for MII modes (10BASE-Te and 100BASE-TX).

The register defaults to 1, which corresponds to bytes. In 10BASE-Te and 100BASE-TX, because the MAC-PHY interface is nibble based, the internal prefill in the transmit

FIFO is larger and is observed as longer latency times. The latency specifications in Table 1 have this bit set to 0.

3 This 100BASE-TX RGMII transmit latency is where the transmit FIFO is programmed for synchronous operation (MAC transmit clock must be synchronous with the

ADIN1300 reference clock), see the FIFO_SYNC register.

4 This 100BASE-TX RGMII transmit latency is where the MAC transmit clock does not have to be synchronous with the ADIN1300 reference clock and the transmit FIFO

takes care of any phase difference.

5 The RMII transmit latency depends on the phase relationship between the 50 MHz reference clock and the internal 25 MHz clock. The transmit latency is fixed for a given

link.

6 Where load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

TIMING CHARACTERISTICS

Rise and fall time specifications are defined from 10% to 90%, unless otherwise noted.

Power-Up Timing

Table 2. Power-Up Timing

Parameter

Description

Min

Typ

Max

Unit

tRAMP

Power supply ramp time

Minimum time interval to internal power good1

6.8

XTAL_I crystal settling time

1.5

XTAL_I external clock settling time

μs

Hardware configuration latch time

μs

Management interface active

1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required.

Figure 2. Power-Up Timing

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