ADIN1300CCPZ-R7 datasheet(88/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 88 of 96

Table 126. Bit Descriptions for GE_CLK_CFG (Continued)

Bits

Bit Name

Description

Reset

Access

GE_REF_CLK_EN

When this bit is set, the 25 MHz reference clock from the crystal oscillator is driven at the CLK25_REF

pin. Note that when an external 50 MHz clock is driven at XTAL_I (for RMII), it is divided by 2, and the

divided 25 MHz reference clock is driven at the CLK25_REF pin.

0x1

R/W

GE_CLK_HRT_RCVR_EN

The PHY provides a digital recovered heartbeat clock. This clock is sourced from either the 25 MHz

reference clock or the 125 MHz recovered clock depending on the mode that the PHY is in and on

the settings of certain registers. Setting GE_CLK_HRT_RCVR_EN causes the subsystem to request the

chip to drive the digital recovered heartbeat clock at the GP_CLK pin.

0x0

R/W

GE_CLK_HRT_FREE_EN

The PHY provides a digital free running heartbeat clock. This clock is sourced either from the 25 MHz

reference clock or the 125 MHz free running clock depending on the mode that the PHY is in and on the

settings of certain registers. Setting GE_CLK_HRT_FREE_EN causes the subsystem to request the chip

to drive the digital free running heartbeat clock at the GP_CLK pin.

0x0

R/W

GE_CLK_25_EN

When this bit is set, the 25 MHz reference clock from the crystal oscillator is driven at the GP_CLK pin

(having been processed through the digital block, and is not as clean as the equivalent clock available at

the CLK25_REF pin).

0x0

R/W

Subsystem RGMII Configuration Register

Address: 0xFF23, Reset: 0x0E07, Name: GE_RGMII_CFG

This register allows the MAC interface RGMII configuration to be controlled.

Table 127. Bit Descriptions for GE_RGMII_CFG

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x1

GE_RGMII_100_LOW_LTNCY_EN

Enable/Disable Low RGMII Latency for 100BASE-TX.

0x1

R/W

1: enable low RGMII latency for 100BASE-TX.

0: disable low RGMII latency for 100BASE-TX.

GE_RGMII_10_LOW_LTNCY_EN

Enable/Disable Low RGMII Latency for 10BASE-T.

0x1

R/W

1: enable low RGMII latency for 10BASE-T.

0: disable low RGMII latency for 10BASE-T.

[8:6]

GE_RGMII_RX_SEL

This field allows the RGMII receive clock delay to be specified in terms of the delay locked

loop (DLL) unit delay (tU = 200 ps).

0x0

R/W

111: 10 × tU + 400 ps.

110: 9 × tU + 400 ps.

101: reserved.

100: reserved.

011: reserved.

010: 7 × tU + 400 ps.

001: 6 × tU + 400 ps.

000: 8 × tU + 400 ps.

[5:3]

GE_RGMII_GTX_SEL

This field allows the RGMII transmit clock delay to be specified in terms of the DLL unit

delay (tU = 200 ps).

0x0

R/W

111: 10 × tU + 400 ps.

110: 9 × tU + 400 ps.

101: reserved.

100: reserved.

011: reserved.

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