ADIN1300CCPZ-R7 datasheet(87/96 Pages) AD

87 / 96 page

Data Sheet

ADIN1300

analog.com

Rev. B | 87 of 96

Table 123. Bit Descriptions for GE_SFT_RST_CFG_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

GE_SFT_RST_CFG_EN

In the event of a subsystem software reset using the GE_SFT_RST bit, the subsystem behavior depends

on the setting of the GE_SFT_RST_CFG_EN bit.

0x0

R/W

1: when the GE_SFT_RST_CFG_EN bit is set, the subsystem requests a new set of hardware configura-

tion pin settings from the chip during the software reset sequence.

0: when GE_SFT_RST_CFG_EN is clear, the previously stored hardware configuration pin settings are

reloaded into the corresponding management registers.

Subsystem Interrupt Enable Register

Address: 0xFF1D, Reset: 0x000E, Name: GE_IRQ_EN

This register is used to control whether or not the interrupt on INT_N hardware pin is asserted in response to various events.

Table 124. Bit Descriptions for GE_IRQ_EN

Bits

Bit Name

Description

Reset

Access

[15:5]

RESERVED

Reserved.

0x0

R/W

GE_HRD_RST_IRQ_EN

This bit enables an interrupt in response to a hardware reset. Note that this bit is initialized

to its pin dependent default value on reset. Therefore, the interrupt is only generated when

the PHY is configured to enter software power-down on exit from reset either through

hardware strapping (Row 4 of Table 25) or alternatively through software configuration (see

Bit GE_PHY_SFT_PD_CFG in the GE_PHY_BASE_CFG register).

0x0

R/W

[3:0]

RESERVED

Reserved.

0xE

R/W

Subsystem Interrupt Status Register

Address: 0xFF1E, Reset: 0x0000, Name: GE_IRQ_LAT

This register is used to check and clear the interrupt on INT_N hardware pin after a hardware reset.

Table 125. Bit Descriptions for GE_IRQ_LAT

Bits

Bit Name

Description

Reset

Access

[15:5]

RESERVED

Reserved.

0x0

GE_HRD_RST

_IRQ_LH

This bit indicates that a hardware reset occurred since the last time this register was read.

0x0

R LH

[3:0]

RESERVED

Reserved.

0x0

Subsystem Clock Configuration Register

Address: 0xFF1F, Reset: 0x0008, Name: GE_CLK_CFG

This register allows the subsystem output clock configuration to be controlled.

Table 126. Bit Descriptions for GE_CLK_CFG

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

GE_CLK_RCVR_125_EN

When this bit is set, the 125 MHz PHY recovered clock (or PLL clock) is driven at the GP_CLK pin.

0x0

R/W

GE_CLK_FREE_125_EN

When this bit is set, the 125 MHz PHY free running clock is driven at the GP_CLK pin.

0x0

R/W

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