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SSM2529ACBZ-R7 Scheda tecnica(PDF) 28 Page - Analog Devices

Il numero della parte SSM2529ACBZ-R7
Spiegazioni elettronici  Digital Input, Mono 2 W, Class-D Audio Power Amplifier
PDF  52 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

SSM2529ACBZ-R7 Scheda tecnica(HTML) 28 Page - Analog Devices

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SSM2529
Data Sheet
Rev. 0 | Page 28 of 52
Input Sample
Frequency, fS (kHz)
Setting 0
b000
Setting 1
b001
Setting 2
b010
Setting 3
b011
Setting 4
b100
Setting 5
b101
Setting 6
b110 thru
b111
48
Ratio
N/A
128 f
S
256 f
S
384 f
S
512 f
S
768 f
S
Reserved
MCLK
6.144 MHz
12.288 MHz
18.432 MHz
24.576 MHz
36.864 MHz
88.2
Ratio
N/A
64 f
S
128 f
S
192 f
S
256 f
S
384 f
S
Reserved
MCLK
5.6448 MHz
11.2896 MHz
16.9344 MHz
22.5792 MHz
33.8688 MHz
96
Ratio
N/A
64 f
S
128 f
S
192 f
S
256 f
S
384 f
S
Reserved
MCLK
6.144 MHz
12.288 MHz
18.432 MHz
24.576 MHz
36.864 MHz
When using MCS = 0/64fS mode, the chip automatically operates in low power mode.
EDGE SPEED AND CLOCKING CONTROL (SYS_CTRL) REGISTER
Table 49. Address: 0x01, Reset: 0x20, Name: SYS_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
PDM_MODE
PDM input enable
0x0
RW
0
Disable PDM input
1
Enable PDM input
6
PDM_FS
PDM input sample rate
0x0
RW
0
About 3 MHz sample rate
1
About 6 MHz sample rate
5
PDB_ADC
ADC power down
0x1
RW
0
Power down
1
Power on
4
BCLK_RATE
BCLK cycles per channel frame
0x0
RW
0
32 cycles per channel
1
16 cycles per channel
3
BCLK_GEN
Generate BCLK internally
0x0
RW
0
Disabled
1
Enabled
[2:1]
EDGE
Edge rate control
0x0
RW
00
Normal operation
01
Low EMI mode operation
0
ASR
Auto sample rate
0x0
RW
0
Sample rate setting determined by MCS register (Register 0x00, Bits[3:1])
1
Automatic sample rate detection
SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL (SAI_FMT1) REGISTER
Table 50. Address: 0x02, Reset: 0x02, Name: SAI_FMT1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SDATA_FMT
Serial data format
0x0
RW
00
I2S, BCLK delay by 1
01
Left justified
10
Right justified, 24-bit data
11
Right justified, 16-bit data
[5:3]
SAI
Serial audio interface format
0x0
RW
000
Stereo I2S, left justified, right justified
001
TDM2
010
TDM4
011
TDM8
100
TDM16
101
Mono PCM
110
Reserved
111
Reserved



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