SSM2529ACBZ-R7 datasheet(19/52 Pages) AD

19 / 52 page

Data Sheet

SSM2529

Rev. 0 | Page 19 of 52

Figure 38 shows a high level system block diagram of the DRC

function.

Figure 38. DRC Block Diagram

Level Measurement

The DRC level measurement includes the peak and rms value

measurements. The parameters that affect the peak measurement

are attack time and release time (AT and RT). The parameter that

affects the rms measurement is average time (TAV). The attack time

can vary from 0 ms to 1.536 sec; the release time and average

time can vary from 0 ms to 24.576 sec. The corresponding bits

are PEAK_ATT, PEAK_REL, and DRCLELTAV and can be found

in Register 0x56 and Register 0x57.

Table 19. DRC_CTRL1 Register

Reserved

DRCLELTAV[3:0]

Table 20. Bit Description of DRC_CTRL1 Register

Bit Name

Description

Settings

DRCLELTAV[3:0]

DRC rms detector

average time

0000: 0 ms

0001: 0.075 ms

0011: 0.30 ms (default)

1111: 24.576 sec

Table 21. DRC_CTRL2 Register

PEAK_ATT[3:0]

PEAK_REL[3:0]

Table 22. Bit Description of DRC_CTRL2 Register

Bit Name

Description

Settings

PEAK_ATT[3:0]

DRC peak detector

attack time

0000: 0 ms

0001: 0.09 ms

0010: 0.19 ms

0011: 0.37 ms

0100: 0.75 ms

0101: 1.5 ms

0110: 3.0 ms

0111: 6.0 ms

…

1111: 1.536 sec

PEAK_REL[3:0]

DRC peak detector

decay time

0000: 0 ms

0001: 1.5 ms

0010: 3 ms

0011: 6 ms

0100: 12 ms

…

1111: 24.576 sec

Static Curve

The static curve is the DRC core function used to define the

targeted input and output relationship. The role for the DRC

block is to find the appropriate gain values with the various signal

levels. To change the dynamic range of the original audio signal,

the gain values vary with the input signal level.

An example of such a static curve is given in Figure 39, which

shows the input and output signal levels. The blue line shows a

linear relationship where the output dynamic range is identical

to the input dynamic range. The red line shows a different output

dynamic range from the input. Furthermore, this curve indicates

that the signal dynamic range is larger when the input signal is low.

Figure 39. DRC Output vs. Input

Figure 40 shows the gain values at various input signal levels.

Figure 40. DRC Gain vs. Input

DRC Static Curve Function

A number of threshold levels (referred to the input) are used in

Figure 39 and Figure 40; these levels are defined as the limiter

threshold (LT), compressor threshold (CT), expander threshold

(ET), noise gate threshold (NT), maximum output signal amplitude

(SMAX), and minimum output signal amplitude (SMIN). The

corresponding bits, DRC_LT, DRC_CT, DRC_ET, DRC_NT,

DRC_SMAX, DRC_SMIN, can be found in Register 0x59 to

LEVEL

MEASUREMENT

STATIC

CURVE

GAIN

SMOOTH

DELAY

yR(n)

DELAY

yL(n)

xR(n)

xL(n)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

INPUT (dBFS)

RELATIONSHIP BETWEEN INPUT AND OUTPUT WITHOUT DRC

RELATIONSHIP BETWEEN INPUT AND OUTPUT WITH DRC

SMAX

SMIN

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

INPUT (dBFS)

DRC GAIN

SSM2529ACBZ-R7 Scheda tecnica(PDF) 19 Page - Analog Devices

SSM2529ACBZ-R7 Scheda tecnica(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Scheda tecnica Scarica

Link URL