SSM2529ACBZ-R7 datasheet(23/52 Pages) AD

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Data Sheet

SSM2529

Rev. 0 | Page 23 of 52

I2C Read and Write Operations

Table 42 shows the timing of a single-word write operation.

Every ninth clock, the SSM2529 issues an acknowledge by

pulling SDA low.

Table 43 shows the timing of a burst mode write sequence as an

example where the target destination registers are two bytes. The

SSM2529 knows to increment its subaddress register every byte

because the requested subaddress corresponds to a register or

memory area with a byte word length.

The timing of a single-word read operation is shown in Table 44.

Note that the first R/W bit is 0, indicating a write operation. This

is because the subaddress still needs to be written to set up the

internal address. After the SSM2529 acknowledges the receipt of

the subaddress, the master must issue a repeated start command

followed by the chip address byte with the R/W bit set to 1 (read).

This causes the SSM2529 SDA to reverse and begin driving data

back to the master. The master then responds every ninth pulse

with an acknowledge pulse to the SSM2529.

Table 42 to Table 45 use the abbreviations shown in Table 41.

Table 41. Symbols for Table 42 to Table 45

Symbol

Meaning

Start bit

Stop bit

Acknowledge by master

Acknowledge by slave

Figure 41. I2C Read and Write Timing

Table 42. Single-Word I2C Write Format

IC Address (7 Bits)

R/W = 0

Subaddress (8 bits)

Data Byte 1 (8 Bits)

Table 43. Burst Mode I2C Write Format

Chip address, R/W = 0

Subaddress

Data-Word 1

Data-Word 2

…

Table 44. Single-Word I2C Read Format

Chip address, R/W = 0

Subaddress

Chip address, R/W = 1

Data Byte 1

Data Byte N

Table 45. Burst Mode I2C Read Format

Chip address, R/W = 0

Subaddress

Chip address, R/W = 1

Data-Word 1

…

SCK

SDA

START BY

MASTER

STOP BY

MASTER

SCK

(CONTINUED)

SDA

(CONTINUED)

FRAME 3

DATA BYTE 1

FRAME 4

DATA BYTE 2

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE

ACK

R/W

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