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SSM2529ACBZ-R7 Scheda tecnica(PDF) 20 Page - Analog Devices |
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SSM2529ACBZ-R7 Scheda tecnica(HTML) 20 Page - Analog Devices |
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20 / 52 page ![]() SSM2529 Data Sheet Rev. 0 | Page 20 of 52 Table 23. DRC_CURVE1 Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved DRC_LT[6:0] Table 24. Bit Description of DRC_CURVE1 Register Bit Name Description Settings DRC_LT[6:0] DRC limiter threshold 0000000: +6 dB 0000001: +5.5 dB −0.5 dB step to 1010000: −35 dB Table 25. DRC_CURVE2 Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved DRC_CT[6:0] Table 26. Bit Description of DRC_CURVE2 Register Bit Name Description Settings DRC_CT[6:0] DRC compressor threshold 0000000: +6 dB 0000001: +5.5 dB −0.5 dB step to 1010000: −35 dB Table 27. DRC_CURVE3 Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved DRC_SMAX[6:0] Table 28. Bit Description of DRC_CURVE3 Register Bit Name Description Settings DRC_SMAX[6:0] DRC maximum output signal amplitude 0000000: +6 dB 0000001: +5.5 dB −0.5 dB step to 1010000: −35 dB Table 29. DRC_CURVE4 Register D7 D6 D5 D4 D3 D2 D1 D0 DRC_NT[3:0] DRC_ET[3:0] Table 30. Bit Description of DRC_CURVE4 Register Bit Name Description Settings DRC_NT[3:0] DRC noise gating threshold 0000: −51 dB 0001: −54 dB −3 dB step to 1111: −96 dB DRC_ET[3:0] DRC expander threshold 0000: −36 dB 0001: −39 dB −3 dB step to 1111: −81 dB Table 31. DRC_CURVE5 Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved DRC_SMIN[3:0] Table 32. Bit Description of DRC_CURVE5 Register Bit Name Description Settings DRC_SMIN[3:0] DRC minimum output signal level 0000: −51 dB 0001: −54 dB −3 dB step to 1111: −96 dB DRC Gain Smooth Before the gain calculated by the static curve function multiplies with the input signal, smooth it to ensure that it does not change rapidly for this can lead to noise. The gain smooth is affected by its attack and decay time parameters. The attack time can vary from 0 ms to 1.536 sec, while the decay time can vary from 0 ms to 24.576 sec. The corresponding bits are DRC_ATT and DRC_DEC and can be found in Register 0x58. Table 33. DRC_CTRL3 Register D7 D6 D5 D4 D3 D2 D1 D0 DRC_ATT[3:0] DRC_DEC[3:0] Table 34. Bit Description of DRC_CTRL3 Register Bit Name Description Settings DRC_ATT[3:0] DRC attack time 0000: 0 ms 0001: 0.1 ms 0010: 0.19 ms 0011: 0.37 ms 0100: 0.75 ms 0101: 1.5 ms 0110: 3 ms 0111: 6 ms … 1111: 1.536 sec DRC_DEC[3:0] DRC decay time 0000: 0 ms 0001: 1.5 ms 0010: 3 ms 0011: 6 ms 0100: 12 ms … 1111: 24.576 sec |
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