SSM2529ACBZ-R7 datasheet(15/52 Pages) AD

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Data Sheet

SSM2529

Rev. 0 | Page 15 of 52

PDM MODE SETUP AND CONTROL

If the ADDR pin is tied to DVDD while in standalone mode, or

the PDM_MODE bit (Register 0x01, Bit 7) is set to 1 while in I2C

mode, the SSM2529 operates in PDM mode. In PDM mode, the

SDATA pin receives the 1-bit PDM input to the DAC, and the

BCLK pin provides the system clock for registering the input data.

The PDM data input is registered directly on each clock edge.

The left or right data can be registered on either the rising or falling

BCLK edge in both standalone mode or in I2C mode by setting

the BCLK_EDGE bit (Register 0x03, Bit 0).

When the part is in standalone mode and the PDM interface is

selected, pull the MCLK pin to logic level low to register the left

channel data (L data) on the rising BCLK edge, and the right

channel data (R data) on the falling BCLK edge. When the

MCLK pin is connected to logic high, the R data is registered

on the rising BCLK edge, and the L data is registered on the

falling BCLK edge.

When this part is in I2C PDM mode, if BCLK_EDGE = 0, the L

data is registered on the rising BCLK edge and the R data is

registered on the falling BCLK edge. If BCLK_EDGE = 1, the L

data is registered on the falling BCLK edge, and the R data is

registered on the rising BCLK edge.

Table 9. PDM Timing Parameters

Parameter

Limit

Unit

Description

TMIN

TMAX

FALL

Clock fall time

RISE

Clock rise time

SETUP

Data setup time

HOLD

Data hold time

Figure 26. PDM Input Format

HIGH-PASS FILTER

The audio processing block contains a configurable first-order,

high-pass filter. When the high-pass filter is enabled, the dc

values are continuously calculated and subtracted from the

input signal. By setting HPFOR (Register 0x15, Bit 1), the last

calculated dc value is stored. When the high-pass filter is

disabled, the stored value is still subtracted from the input

signal until the HPFOR is cleared to 0.

The high-pass filter can work in audio mode or application

mode, as configured by the HPF_CTRL register. In audio mode,

the high-pass filter’s 3 dB cutoff frequency is 3.7 Hz when the

sampling rate is 48 kHz. In application mode, the 3 dB cutoff

frequency varies from 50 Hz to 750 Hz, which is selected by using

the HPFCUT bits (Register 0x15, Bits[5:2]).

Figure 27. High-Pass Filter Response from HPFCUT Adjustment

Table 10. HPF_CTRL Register

Reserved

HPFCUT

HPFOR

HPFEN

Table 11. Bit Description of HPF_CTRL Register

Bit Name

Description

Settings

HPFCUT[3:0]

HPF cut-off

frequency selection

See the Table 66

HPFOR

HPF mode selection

0: audio mode (cutoff

frequency is 3.7 Hz)

1: application mode (cut-

off frequency selectable)

HPFEN

HPF enable

0: disable

1: enable

FULLY PROGRAMMABLE SEVEN-BAND EQUALIZER

The programmable seven-band equalizer comprises five biquad

filters (Band 1 to Band 5) and two first-order IIR filters (Band 6

and Band 7). Figure 28 shows the system block diagram.

All filter coefficients are programmable via the corresponding

registers. When not all five midfrequency bands are needed, the

filter bank can be configured as other filters, such as de-emphasis

and notch filters.

To operate as a seven-band equalizer, the two first-order IIR filters

are usually configured as one low-pass shelving filter and one high-

pass shelving filter, and the biquad filters are configured as peak

filters. By using the coefficient registers, the cutoff frequencies

and peak gains of the shelving filters and the center frequencies and

bandwidths of the peak filters are programmable. For frequency

bands lower than 200 Hz, the low-pass shelving filter is suggested.

Figure 28. System Block Diagram

BCLK

SDATA

DATA

tHOLD

tSETUP

DATA

–60

–50

–40

–30

–20

–10

100

200

300

400

500

600

700

800

900

1000

FREQUENCY (kHz)

BIQUAD1

BIQUAD2

BIQUAD3

BIQUAD4

BIQUAD5

FIRST ORDER

IIR 1

FIRST ORDER

IIR 1

SEVEN-BAND EQUALIZER

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