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SSM2529ACBZ-R7 Scheda tecnica(PDF) 24 Page - Analog Devices |
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SSM2529ACBZ-R7 Scheda tecnica(HTML) 24 Page - Analog Devices |
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24 / 52 page  SSM2529 Data Sheet Rev. 0 | Page 24 of 52 REGISTER SUMMARY The SSM2529 contains eighteen 8-bit registers that can be accessed via the I2C port. See Table 46 for the control register mapping. The register settings are described in detail in Table 47 through Table 159. Table 46. Hex Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 00 PWR_CTRL [7:0] SYS_RST APWDN_ANA APWDN_EN LP_MODE MCS SPWDN 0x23 RW 01 SYS_CTRL [7:0] PDM_MODE PDM_FS PDB_ADC BCLK_RATE BCLK_GEN EDGE ASR 0x20 RW 02 SAI_FMT1 [7:0] SDATA_FMT SAI SR 0x02 RW 03 SAI_FMT2 [7:0] LPST LR_SEL LRCLK_MODE LRCLK_POL SAI_MSB BCLK_TDMC BCLK_EDGE 0x00 RW 04 Channel mapping control [7:0] CH_SEL_R CH_SEL_L 0x10 RW 05 VOL_BF_FDSP [7:0] DIG_VOL 0x40 RW 06 VOL_AF_FDSP [7:0] PDP_VOL 0x40 RW 07 Volume and mute control [7:0] CLK_LOSS_DET SR_AUTO Reserved PDP_VOL_ FORCE DIG_VOL_ FORCE ANA_GAIN 0x20 RW 08 DPLL_CTRL [7:0] Reserved DPLL_REF_SEL DPLL_NDIV 0x00 RW 09 APLL_CTRL1 [7:0] M_HI 0x00 RW 0A APLL_CTRL2 [7:0] M_LO 0x00 RW 0B APLL_CTRL3 [7:0] N_HI 0x00 RW 0C APLL_CTRL4 [7:0] N_LO 0x00 RW 0D APLL_CTRL5 [7:0] Reserved R X Type 0x00 RW 0E APLL_CTRL6 [7:0] FSYS_DPLL DPLL_BYPASS APLL_BYPASS DPLL_LOCK APLL_LOCK PLLEN COREN 0x30 RW 0F FAULT_CTRL1 [7:0] Reserved PDB_LINE PDB_ZC CLK_LOSS OC OT 0x000 RW 10 FAULT_CTRL2 [7:0] Reserved AR_TIME MRCV MAX_AR ARCV 0x4C RW 14 DEEMP_CTRL [7:0] Reserved DEEMP_FS DEEMP_EN 0x00 RW 15 HPF_CTRL [7:0] Reserved HPFCUT HPFOR HPFEN 0x00 RW 16 EQ1_COEF0_HI [7:0] EQ1_COEF0_HI 0x00 RW 17 EQ1_COEF0_LO [7:0] EQ1_COEF0_LO 0x00 RW 18 EQ1_COEF1_HI [7:0] EQ1_COEF1_HI 0x00 RW 19 EQ1_COEF1_LO [7:0] EQ1_COEF1_LO 0x00 RW 1A EQ1_COEF2_HI [7:0] EQ1_COEF2_HI 0x00 RW 1B EQ1_COEF2_LO [7:0] EQ1_COEF2_LO 0x00 RW 1C EQ1_COEF3_HI [7:0] EQ1_COEF3_HI 0x00 RW 1D EQ1_COEF3_LO [7:0] EQ1_COEF3_LO 0x00 RW 1E EQ1_COEF4_HI [7:0] EQ1_COEF4_HI 0x00 RW 1F EQ1_COEF4_LO [7:0] EQ1_COEF4_LO 0x00 RW 20 EQ2_COEF0_HI [7:0] EQ2_COEF0_HI 0x00 RW 21 EQ2_COEF0_LO [7:0] EQ2_COEF0_LO 0x00 RW 22 EQ2_COEF1_HI [7:0] EQ2_COEF1_HI 0x00 RW 23 EQ2_COEF1_LO [7:0] EQ2_COEF1_LO 0x00 RW 24 EQ2_COEF2_HI [7:0] EQ2_COEF2_HI 0x00 RW 25 EQ2_COEF2_LO [7:0] EQ2_COEF2_LO 0x00 RW 26 EQ2_COEF3_HI [7:0] EQ2_COEF3_HI 0x00 RW 27 EQ2_COEF3_LO [7:0] EQ2_COEF3_LO 0x00 RW 28 EQ2_COEF4_HI [7:0] EQ2_COEF4_HI 0x00 RW 29 EQ2_COEF4_LO [7:0] EQ2_COEF4_LO 0x00 RW 2A EQ3_COEF0_HI [7:0] EQ3_COEF0_HI 0x00 RW 2B EQ3_COEF0_LO [7:0] EQ3_COEF0_LO 0x00 RW 2C EQ3_COEF1_HI [7:0] EQ3_COEF1_HI 0x00 RW 2D EQ3_COEF1_LO [7:0] EQ3_COEF1_LO 0x00 RW 2E EQ3_COEF2_HI [7:0] EQ3_COEF2_HI 0x00 RW 2F EQ3_COEF2_LO [7:0] EQ3_COEF2_LO 0x00 RW 30 EQ3_COEF3_HI [7:0] EQ3_COEF3_HI 0x00 RW 31 EQ3_COEF3_LO [7:0] EQ3_COEF3_LO 0x00 RW 32 EQ3_COEF4_HI [7:0] EQ3_COEF4_HI 0x00 RW 33 EQ3_COEF4_LO [7:0] EQ3_COEF4_LO 0x00 RW 34 EQ4_COEF0_HI [7:0] EQ4_COEF0_HI 0x00 RW 35 EQ4_COEF0_LO [7:0] EQ4_COEF0_LO 0x00 RW 36 EQ4_COEF1_HI [7:0] EQ4_COEF1_HI 0x00 RW |
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