SSM2529ACBZ-R7 datasheet(14/52 Pages) AD

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SSM2529

Data Sheet

Rev. 0 | Page 14 of 52

THEORY OF OPERATION

OVERVIEW

The SSM2529 is a fully integrated, mono, digital switching audio

amplifier. The SSM2529 receives digital audio inputs and produces

the PDM differential switching outputs using the internal power

stage. The part has built-in protections for overtemperature and

overcurrent conditions. The SSM2529 also has built-in soft

turn-on and soft turn-off for pop-and-click suppression. The part

has programmable register control via the I2C port.

MASTER CLOCK

In master mode, the built-in PLL can provide the master clock. In

slave mode, the SSM2529 receives an external clock at the

MCLK or BCLK input pin. The external clock must be fully

synchronous with the incoming digital audio on the serial

interface. The internal clock for the SSM2529 always runs at

5.6448 MHz to 8.192 MHz, depending on the input sample rate.

The three options for providing the master clock to the part are as

follows:

•

Using the clock generated by the built-in PLL

•

Using the BCLK pin

•

Using the MCLK pin

The MCLK option can use the built-in PLL or the BCLK pin to

generate the internal clock as long as the clock is provided at the

same rate that is required by the MCLK pin. By setting the PLLEN

bit in Register 0x0E, this is enabled. In this case, there is no need to

provide the master clock to the MCLK pin, which in turn saves a

pin connection from the audio source. If using the MCLK pin,

various multiples of the sample frequency can be used for MCLK.

See Table 48 for all available options and settings. When the

SSM2529 enters its power-down state, it is possible to gate this

clock to further conserve system power. However, an MCLK

must be present for the audio amplifier to operate. The input

MCLK rate is determined by setting the MCS bits in Register 0x00.

For more information, see Table 48.

INTERNAL CLOCK GENERATOR

The digital core clock can be derived directly from the external

clock, or it can be generated using the PLL. Clocks for the DSPs,

the serial ports, and the converters are derived from the core clock.

The core clock rate is always an integer multiple of the sample

rate used for the part.

The clock generation block is composed of a digital PLL and an

analog PLL. The analog PLL can accept input frequencies in the

8 MHz to 27 MHz range. To support lower frequencies (8 kHz

to 8 MHz), the chip provides a digital PLL. It can boost the

input clock frequency by 2N, where N = 1 to 10.

Figure 25 shows the clock generation block diagram.

For the digital PLL, the source clock is selected by the

DPLL_REF_SEL bits (Register 0x08), and the frequency

relationship between the DPLL input and the output clock is

defined by the DPLL_NDIV bit.

The frequency relationship between the APLL input and output is

fPLL = fIN ×(R + (N/M))/X

where R, N, M, and X are defined by the corresponding PLL

registers (Register 0x09 to Register 0x0D).

DIGITAL INPUT SERIAL AUDIO INTERFACE

The SSM2529 includes a standard serial audio interface that is

slave only. The interface is capable of receiving I2S, left justified,

right justified, PCM/TDM, or PDM input formats. The number

of data bits must be set when in right-justified mode only.

Figure 25. Clock Generation Block Diagram

÷X

APLL

CLK_IN × 2N

CLOCK HIGHER

THAN 8MHz

ANALOG PLL

DIGITAL PLL

×2N

N = 1 TO 10

CLK_IN

LRCLK/BCLK

44.4kHz × 1024/

48kHz × 1024

×(R + N/M)

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