SSM2529ACBZ-R7 datasheet(22/52 Pages) AD

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SSM2529

Data Sheet

Rev. 0 | Page 22 of 52

POWER-ON RESET/VOLTAGE SUPERVISOR

The SSM2529 includes an internal power-on reset and voltage

supervisor circuit. This circuit provides an internal reset to all

circuitry during initial power-up. It also monitors the power

supplies to the IC, and it mutes the outputs and issues a reset

when the voltages are lower than the minimum operating range.

This ensures that no damage due to low voltage operation occurs

and that no pops can occur under nearly any power removal

conditions.

STANDALONE MODE

When the SA_MODE pin is pulled high, the SSM2529 can operate

without any I2C control. In this mode, the automatic sample rate

detection and smart power-down are always enabled. Volume

Control A and Volume Control B can be controlled via the SCL

and SDA pins.

In standalone mode, the DRC function is disabled. The EQ and

HPF are also disabled. When ADDR = 1, the input interface is

PDM. Otherwise, I2S and TDM serial interface formats can be

selected via MCLK. In standalone mode, the working clock is

generated by the internal PLL.

Table 39. Standalone Mode Pin Configuration

Conventional

Operation Pin

SA_MODE = 1

SCL

Volume Control A

SDA

Volume Control B

STDBN

0: shutdown/mute

1: normal operation

ADDR

1: PDM

0: I2S/TDM

BCLK

0: 16 BCLK cycles provided by PLL

1: 32 BCLK cycles provided by PLL

Clock: 32 BCLK cycles provided off chip

MCLK

0: I2S (ADDR = 0) or PDM L channel (ADDR = 1)

1: TDM (ADDR = 0) or PDM R channel (ADDR = 1)

I2C PORT

The SSM2529 supports a 2-wire serial (I2C-compatible) micro-

processor bus driving multiple peripherals. Two pins, serial data

(SDA) and serial clock (SCL), carry information between the

SSM2529 and the system I2C master controller. The SSM2529 is

always a slave on the bus, meaning that it cannot initiate a data

transfer. Each slave device is recognized by a unique address. The

address byte format is shown in Table 40. The address resides in

the first seven bits of the I2C write. The LSB of this byte either

sets a read or write operation. Logic Level 1 corresponds to a read

operation, and Logic Level 0 corresponds to a write operation The

full byte addresses are shown in Figure 41, where the subaddresses

are automatically incremented at word boundaries, and can be

used for writing large amounts of data to contiguous memory

locations. This increment happens automatically after a single-

word write unless a stop condition is encountered. A data

transfer is always terminated by a stop condition.

Both SDA and SCL must have a 2.2 kΩ pull-up resistor on the lines

connected to them. The voltage on these signal lines must not

be more than 3.6 V.

Table 40. I2C Address Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

R/W

Addressing

Initially, each device on the I2C bus is in an idle state, monitoring

the SDA and SCL lines for a start condition and the proper address.

The I2C master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA, while

SCL remains high. This indicates that an address/data stream

follows. All devices on the bus respond to the start condition

and shift the next eight bits (the 7-bit address plus the R/W bit)

MSB first. The device that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. The device address for the SSM2529 is 0x34. The ninth bit

is known as the acknowledge bit. All other devices withdraw from

the bus at this point and return to the idle condition.

The R/W bit determines the direction of the data. A Logic 0 on the

LSB of the first byte means that the master writes information to

the peripheral, whereas a Logic 1 means that the master reads

information from the peripheral after writing the subaddress and

repeating the start address. A data transfer takes place until a

stop condition is encountered. A stop condition occurs when

SDA transitions from low to high while SCL is held high. The

timing for the I2C port is shown in Figure 3.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the SSM2529 immediately

jumps to the idle condition. During an SCL high period, issue only

one start condition, one stop condition, or a single stop condition

followed by a single start condition. If an invalid subaddress is

issued, the SSM2529 does not issue an acknowledge and returns to

the idle condition. If the highest subaddress is exceeded while in

auto-increment mode, one of two actions is taken. In read mode,

the SSM2529 outputs the highest subaddress register contents

until the master device issues a no acknowledge, indicating the

end of the read. When the SDA line is not pulled low on the

ninth clock pulse of SCL, a no acknowledge occurs. If the

highest subaddress location is reached while in write mode, the

data for the invalid byte is not loaded into any subaddress

part returns to the idle condition.

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