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SSM2529ACBZ-R7 Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte SSM2529ACBZ-R7
Spiegazioni elettronici  Digital Input, Mono 2 W, Class-D Audio Power Amplifier
PDF  52 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

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SSM2529
Data Sheet
Rev. 0 | Page 6 of 52
POWER SUPPLY REQUIREMENTS
Table 2.
Parameter
Min
Typ
Max
Unit
SPKVDD
2.5
4.2
5.5
V
DVDD
1.08
1.8
1.98
V
DIGITAL INPUT/OUTPUT
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Input Voltage, High
V
IH
0.7 × DVDD
3.6
V
Input Voltage, Low
V
IL
−0.3
+0.3 × DVDD
V
Input Leakage Current, High
I
IH
Excluding MCLK
1
µA
Input Leakage Current, Low
I
IL
Excluding MCLK and bidirectional pins
1
µA
MCLK Input Leakage, High
I
IH
3
µA
MCLK Input Leakage, Low
I
IL
3
µA
Input Capacitance
5
pF
DIGITAL INTERPOLATION FILTER
Table 4.
Parameter
Mode
Factor
Min
Typ
Max
Unit
Pass Band (−3 dB)
48 kHz mode, typical at 48 kHz
0.423 f
S
20
kHz
Pass-Band Ripple
48 kHz mode, typical at 48 kHz
0.5 f
S
±0.03
dB
Transition Band
48 kHz mode, typical at 48 kHz
24
kHz
Stop Band
48 kHz mode, typical at 48 kHz
0.582 f
S
28
kHz
Stop Band Attenuation
48 kHz mode, typical at 48 kHz
60
dB
Group Delay
48 kHz mode, typical at 48 kHz
14/f
S
292
µs
DIGITAL TIMING
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 5.
Limit
Parameter
T
MIN
T
MAX
Unit
Description
MASTER CLOCK (See Figure 2)
t
BP
74
136
ns
MCLK period, 256 f
S mode
t
BP
148
271
ns
MCLK period, 128 f
S mode
SERIAL PORT (See Figure 2)
t
BIL
40
ns
BCLK low pulse width
t
BIH
40
ns
BCLK high pulse width
t
LIS
10
ns
LRCLK setup; time to BCLK rising
t
LIH
10
ns
LRCLK hold; time from BCLK rising
t
SIS
10
ns
SDATA setup; time to BCLK rising
t
SIH
10
ns
SDATA hold; time from BCLK rising



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