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AT83SND1CXXX-ROTIL Scheda tecnica(PDF) 131 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL Scheda tecnica(HTML) 131 Page - ATMEL Corporation |
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131 / 212 page ![]() 131 4109J–8051–10/06 AT8xC51SND1C Figure 16-2. IDE Write Waveforms Notes: 1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out- puts SFR content instead of DPH. 16.1.1 IDE Device Connection Figure 16-3 and Figure 16-4 show 2 examples on how to interface up to 2 IDE devices to the AT8xC51SND1C. In both examples P0 carries IDE low order data bits D7:0, P2 carries IDE high order data bits D15:8, while RD and WR signals are respectively connected to the IDE nIOR and nIOW signals. Other IDE control signals are generated by the external address latch outputs in the first example while they are generated by some port I/Os in the second one. Using an exter- nal latch will achieve higher transfer rate. Figure 16-3. IDE Device Connection Example 1 Figure 16-4. IDE Device Connection Example 2 ALE P0 P2 WR(1) DPL or Ri D7:0 P2 CPU Clock DPH or P2 (2),(3) D15:8 P2 P2 P0 D15-8 A2:0 ALE nIOW nIOR RD WR D7:0 nCS1:0 nRESET D15-8 A2:0 nIOW nIOR D7:0 nCS1:0 nRESET Latch IDE Device 0 IDE Device 1 AT8xC51SND1C Px.y P2/A15:8 P0/AD7:0 D15-8 A2:0 P4.5 nIOW nIOR RD WR D7:0 nCS1:0 nRESET D15-8 A2:0 nIOW nIOR D7:0 nCS1:0 nRESET P4.2:0 P4.4:3 IDE Device 0 AT8xC51SND1C IDE Device 1 |
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