AT83SND1CXXX-ROTIL datasheet(134/212 Pages) ATMEL

134 / 212 page

134

4109J–8051–10/06

AT8xC51SND1C

Figure 17-1. Timer 1 Baud Rate Generator Block Diagram

17.2.2

Internal Baud Rate Generator

When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the

timer. As shown in Figure 17-2 the Internal Baud Rate Generator is an 8-bit auto-reload timer

fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in

BDRCON register (see Table 119). The Internal Baud Rate Generator is enabled by setting BBR

bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud

rate.

Figure 17-2. Internal Baud Rate Generator Block Diagram

17.3

Synchronous Mode (Mode 0)

Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabil-

ities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock

pulses while the receive data (RXD) pin transmits or receives a Byte of data. The 8-bit data are

transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see

Section "Baud Rate Selection (Mode 0)", page 136). Figure 17-3 shows the serial port block dia-

gram in Mode 0.

TR1

TCON.6

GATE1

TMOD.7

Overflow

C/T1#

TMOD.6

TL1

(8 bits)

TH1

(8 bits)

INT1

PER

CLOCK

÷ 6

SMOD1

PCON.7

÷ 2

CLOCK

To serial

Port

Overflow

SPD

BDRCON.1

BRG

(8 bits)

BRL

(8 bits)

PER

CLOCK

÷ 6

IBRG

CLOCK

BRR

BDRCON.4

SMOD1

PCON.7

÷ 2

To serial

Port

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