AT83SND1CXXX-ROTIL datasheet(137/212 Pages) ATMEL

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137

4109J–8051–10/06

AT8xC51SND1C

Figure 17-9. Data Frame Format (Mode 1)

17.4.0.2

Modes 2 and 3

Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 17-10) con-

sists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one

programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and

received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On

transmit, the ninth data bit is written to TB8 bit in SCON register. Alternatively, you can use the

ninth bit can be used as a command/data flag.

Figure 17-10. Data Frame Format (Modes 2 and 3)

17.4.1

Transmission (Modes 1, 2

and 3)

To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according to

Table 113, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be transmitted to

SBUF register starts the transmission.

17.4.2

Reception (Modes 1, 2 and 3)

To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to

Table 113, and set the REN bit. The actual reception is then initiated by a detected high-to-low

transition on the RXD pin.

17.4.3

Framing Error Detection (Modes 1, 2 and 3)

Framing error detection is provided for the three asynchronous modes. To enable the framing bit

error detection feature, set SMOD0 bit in PCON register as shown in Figure 17-11.

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.

An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by

2 devices. If a valid stop bit is not found, the software sets FE bit in SCON register.

Software may examine FE bit after each reception to check for data errors. Once set, only soft-

ware or a chip reset clear FE bit. Subsequently received frames with valid stop bits cannot clear

FE bit. When the framing error detection feature is enabled, RI rises on stop bit instead of the

last data bit as detailed in Figure 17-17.

Figure 17-11. Framing Error Block Diagram

Mode 1

Start bit

8-bit data

Stop bit

Start bit

9-bit data

Stop bit

SM0

SMOD0

PCON.6

SM0/FE

SCON.7

Framing Error

Controller

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