PIIX3 datasheet(80/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit 2

Bit 0

Description:

Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data

to/from memory. Specifics of the error have to be determined using bus-specific

information. If the Error bit is 0, the PRD’s specified a smaller size than the IDE

transfer size.

2.7.3.

BMIDTP—BUS MASTER IDE DESCRIPTOR TABLE POINTER REGISTER

Address Offset:

Primary Channel—Base + 04h; Secondary Channel—Base + 0Ch

Default Value:

00000000h

Attribute:

Read/Write

This register provides the base memory address of the descriptor table. The Descriptor Table must be Dword

aligned and not cross a 4-Kbyte boundary in memory.

Bit

Description

31:2

Descriptor Table Base Address. Bits [31:2] correspond to A[31:2].

1:0

Reserved.

2.8.

USB I/O Registers

This section describes the block of USB registers that are located in normal I/O space. The “base” portion of

the I/O address is selected via a PCI Configuration register.

2.8.1.

USBCMD

USB Command Register

I/O Address:

Base+ (00

−01h)

Default Value:

0000h

Attribute:

Read/Write

The Command Register indicates the command to be executed by the serial bus host/hub controller. Writing

to the register causes a command to be executed.

Bit

Description

15:8

Reserved.

Max Packet (MAXP). 1=64 bytes. 0=32 bytes. This bit selects the maximum packet size that

can be used for full speed bandwidth reclamation at the end of a frame. This value is used by

the Host Controller to determine whether it should initiate another transaction based on the

time remaining in the SOF counter. Use of reclamation packets larger than the programmed

size will cause a Babble error if executed during the critical window at frame end. The Babble

error results in the offending endpoint being stalled. Software is responsible for ensuring that

any packet that could be executed under bandwidth reclamation be within this size limit.

Configure Flag (CF). Software sets this bit as the last action in its process of configuring the

Host Controller. This bit has no effect on the hardware. It is provided only as a semaphore

service for software.

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