PIIX3 datasheet(44/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

APMC Write SMI Enable. 1=Enable; 0=Disable.

EXTSMI# SMI Enable. 1=Enable; 0=Disable.

Fast Off Timer SMI Enable. 1=Enable; 0=Disable. When enabled, the timer generates an

SMI when it decrements to zero.

IRQ12 SMI Enable (PS/2 Mouse Interrupt). 1=Enable; 0=Disable.

IRQ8 SMI Enable (RTC Alarm Interrupt). 1=Enable; 0=Disable.

IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse). 1=Enable; 0=Disable.

IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse). 1=Enable; 0=Disable.

IRQ1 SMI Enable (Keyboard Interrupt). 1=Enable; 0=Disable.

2.2.20.

SEE—SYSTEM EVENT ENABLE REGISTER (Function 0)

Address Offset:

A4–A7h

Default Value:

00000000h

Attribute:

Read/Write

This register enables hardware events as system events and break events for power management control.

The default for each system/break event in this register is disabled.

System events: Activity by these events can keep the system from powering down. When a system event is

enabled, the corresponding hardware event activity prevents a Fast Off powerdown condition by reloading the

Fast Off Timer with its initial count.

Break events: These events can awaken a powered down system. When a break event is enabled, the

corresponding hardware event activity powers up the system by negating STPCLK#.

Bit

Description

Fast Off SMI Enable (FSMIEN). 1=Enable (system and break events); 0=Disable.

INTR Enable (FINTREN). 1=Enable (break event); 0=Disable. When enabled, INTR is used

as a global break event. In this case, any IRQ that is generated causes the system to

powerup via the negation of STPCLK#, regardless of the state of bits[15:3,1:0] in this

For the PIIX3, this function should be disabled if an external IOAPIC is used.

Fast Off NMI Enable (FNMIEN). 1=Enable (system and break events); 0=Disable.

82371FB PIIX: Reserved.

PIIX3: Fast Off APIC Enable (FAPICEN). 1=Enable (break event); 0=Disable.

27:16

Reserved

15:3

Fast Off IRQ[15:3] Enable (FIRQ[15:3]EN). 1=Enable (system and break events);

0=Disable.

Reserved.

1:0

Fast Off IRQ[1:0] Enable (FIRQ[1:0]EN). 1=Enable (system and break events); 0=Disable.

PIIX3 Scheda tecnica(PDF) 44 Page - Intel Corporation

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