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PIIX3 Scheda tecnica(PDF) 24 Page - Intel Corporation |
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PIIX3 Scheda tecnica(HTML) 24 Page - Intel Corporation |
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24 / 122 page ![]() 82371FB (PIIX) AND 82371SB (PIIX3) E 24 Configuration Offset Mnemonic Register Register Access 0F–4Bh — Reserved — 4Ch IORT ISA I/O Controller Recovery Timer R/W 4Dh — Reserved — 4Eh (PIIX) 4E–4Fh (PIIX3) XBCS X-Bus Chip Select Enable R/W 4F–5Fh (PIIX) 50–5Fh (PIIX3) — Reserved — 60–63h PIRQRC[A:D] PCI IRQ Route Control R/W 64–68h — Reserved — 69h TOM Top of Memory R/W 6A–6Bh MSTAT Miscellaneous Status R/W 6C–6Fh — Reserved — 70h MBIRQ0 Motherboard IRQ Route Control 0 R/W 71h MBIRQ1 Motherboard IRQ Route Control 1 (PIIX) R/W — Reserved (PIIX3) — 72–75h — Reserved — 76–77h MBDMA[1:0] Motherboard DMA Control R/W 78–79h PCSC Programmable Chip Select Control R/W 7A–7Fh — Reserved — 80h — Reserved (PIIX) — APICBASE APIC Base Address Relocation (PIIX3) R/W 81h — Reserved — 82h — Reserved (PIIX) — DLC Deterministic Latency Control (PIIX3) R/W 83–9Fh — Reserved — A0h SMICNTL SMI Control R/W A1h — Reserved — A2–A3h SMIEN SMI Enable R/W A4–A7h SEE System Event Enable R/W A8h FTMR Fast Off Timer R/W A9h — Reserved — AA–ABh SMIREQ SMI Request R/W |
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