PIIX3 datasheet(30/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Table 6. PCI Bus Master IDE I/O Registers

Offset

From Base

Address

Mnemonic

Access

00h

BMICP

Bus Master IDE Command (primary)

R/W

01h

—

Reserved

—

02h

BMISP

Bus Master IDE Status (primary)

R/WC

03h

—

Reserved

—

04–07h

BMIDTPP

Bus Master IDE Descriptor Table Pointer (primary)

R/W

08h

BMICS

Bus Master IDE Command (secondary)

R/W

09h

—

Reserved

—

0Ah

BMISS

Bus Master IDE Status (secondary)

R/WC

0Bh

—

Reserved

—

0C–0Fh

BMIDTPS

Bus Master IDE Descriptor Table Pointer (secondary)

R/W

NOTE:

The base address is programmable via the BMIBA Register (20

−23h; function 1)

Table 7. USB Host/Controller I/O Registers

I/O Address

Mnemonic

Access

Base + (00

−01h)

USBCMD

USB Command

R/W

Base + (02

−03h)

USBSTS

USB Status

R/WC

Base + (04

−05h)

USBINTR

USB Interrupt Enable

R/W

Base + (06

−07h)

FRNUM

Frame Number

R/W**

Base + (08

−0Bh)

FRBASEADD

Frame List Base Address

R/W

Base + 0Ch

SOFMOD

Start Of Frame Modify

R/W

Base + (10

−11h)

PORTSC1

Port 1 Status/Control

R/WC**

Base + (12

−13h)

PORTSC2

Port 2 Status/Control

R/WC**

** NOTE: These registers are WORD writeable only.

Byte writes to these registers have unpredictable

effects.

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