PIIX3 datasheet(73/122 Pages) INTEL

73 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

2:0

Interrupt Level Select (L2, L1, L0). L2, L1, and L0 determine the interrupt level acted upon

when the SL bit is active (bit 6). When the SL bit is inactive, bits [2:0] do not have a defined

function; programming L2, L1 and L0 to 0 is sufficient in this case.

Bit[2:0]

Interrupt Level

Bit[2:0]

Interrupt Level

000

IRQ 0(8)

100

IRQ 4(12)

001

IRQ 1(9)

101

IRQ 5(13)

010

IRQ 2(10)

110

IRQ 6(14)

011

IRQ 3(11)

111

IRQ 7(15)

2.5.3.8.

OCW3—Operational Control Word 3 Register

I/O Address:

INT CNTRL-1—020h; INT CNTRL-2—0A0h

Default Value:

Bit[6,0]=0; Bit[7,4:2]=Undefined; Bit[5,1]=1

Attribute:

Read/Write

OCW3 serves three important functions—Enable Special Mask Mode, Poll Mode control, and IRR/ISR

Bit

Description

Reserved. Must be 0.

Special Mask Mode (SMM). If ESMM=1 and SMM=1, the interrupt controller enters Special

Mask Mode. If ESMM=1 and SMM=0, the interrupt controller is in normal mask mode. When

ESMM=0, SMM has no effect.

Enable Special Mask Mode (ESMM). 1=Enable SMM bit; 0=Disable SMM bit.

4:3

OCW3 Select. Must be programmed to 01 selecting OCW3.

Poll Mode Command. 0=Disable Poll Mode Command. When bit 2=1, the next I/O read to

the interrupt controller is treated as an interrupt acknowledge cycle indicating highest priority

request..

1:0

and the Interrupt Request Register (IRR). When bit 1=0, bit 0 doesl not affect the register read

selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If

bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the

default OCW3 port address read will be "read IRR". To retain the current selection (read ISR or

read IRR), always write a 0 to bit 1 when programming this register. The selected register can

be read repeatedly without reprogramming OCW3. To select a new status register, OCW3

must be reprogrammed prior to attempting the read.

Bit[1:0]

Function

No Action

Read IRQ Register

Read IS Register

PIIX3 Scheda tecnica(PDF) 73 Page - Intel Corporation

PIIX3 Scheda tecnica(HTML) 73 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL