PIIX3 datasheet(69/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

Count Register Status. This bit indicates when the last count written to the Count Register

(CR) has been loaded into the counting element (CE). 0=Count has been transferred from CR

to CE and is available for reading. 1=Count has not been transferred from CR to CE and is not

yet available for reading.

5:4

Read/Write Selection Status. Bits[5:4] reflect the read/write selection made through bits[5:4]

of the Control Register.

Bit[5:4]

Function

Counter Latch Command

R/W Least Significant Byte (LSB)

R/W Most Significant Byte (MSB)

R/W LSB then MSB

3:1

Mode Selection Status. Bits[3:1] return the counter mode programming.

Bit[3:1]

Mode Selected

Bit[3:1]

Mode Selected

000

X11

001

100

X10

101

Countdown Type Status. 0=Binary countdown; 1=Binary coded decimal (BCD) countdown.

2.5.2.3.

Counter Access Ports Register

I/O Address:

Counter 0—040h; Counter 1—041h; Counter 2—042h

Default Value:

All bits undefined

Attribute:

Read/Write

Each of these I/O ports is used for writing count values to the Count Registers; reading the current count

value from the counter by either an I/O read, after a counter-latch command, or after a Read Back Command;

and reading the status byte following a Read Back Command.

Bit

Description

7:0

Counter Port bit[x]. Each counter I/O port address is used to program the 16-bit Count

with the Interval Counter Control Register. The counter I/O port is also used to read the current

count from the Count Register and return counter programming status following a Read Back

Command.

2.5.3.

INTERRUPT CONTROLLER REGISTERS

The PIIX/PIIX3 contains an ISA-Compatible interrupt controller that incorporates the functionality of two

82C59 interrupt controllers. The interrupt registers control the operation of the interrupt controller.

PIIX3 Scheda tecnica(PDF) 69 Page - Intel Corporation

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