PIIX3 datasheet(61/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.5.

ISA-Compatible Registers

The ISA-Compatible registers contain the DMA, timer/counter, and interrupt registers. This group also

contains the X-Bus, coprocessor, NMI, and reset registers.

2.5.1.

DMA REGISTERS

The PIIX/PIIX3 contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers

(DMA1 and DMA2). The DMA registers control the operation of the DMA controllers and are all

accessible from the Host CPU via the PCI Bus interface. In addition, some of the registers are

accessed from the ISA Bus via ISA I/O space. Unless otherwise stated, a CPURST sets each register

to its default value.

2.5.1.1.

DCOM—DMA Command Register

I/O Address:

Channels 0-3—08h; Channels 4-7—0D0h

Default Value:

00h (CPURST or Master Clear)

Attribute:

Write Only

This 8-bit register controls the configuration of the DMA. Note that disabling channels 4-7 also disables

channels 0-3, since channels 0-3 are cascaded onto channel 4.

Bit

Description

DACK# ACTIVE Level (DACK#[3:0, (7:5)]). 1=Active high; 0=Active low.

DREQ Sense Assert Level (DREQ[3:0, (7:5)]). 1=Active Low; 0=Active high.

Reserved. Must be 0.

DMA Group Arbitration Priority. 1=Rotating priority; 0=Fixed priority

Reserved. Must be 0

DMA Channel Group Enable. 1=Disable; 0 = Enable.

1:0

Reserved. Must be 0.

2.5.1.2.

DCM—DMA Channel Mode Register

I/O Address:

Channels 0-3=0Bh; Channels 4-7=0D6h

Default Value:

Bits[7:2]=0; Bits[1:0]=undefined (CPURST or Master Clear)

Attribute:

Write Only

Each channel has a 6-bit DMA Channel Mode Register. The Channel Mode Registers provide control

over DMA transfer type, transfer mode, address increment/decrement, and autoinitialization.

Bit

Description

7:6

DMA Transfer Mode. Each DMA channel can be programmed in one of four different modes:

Bits[7:6]

Transfer Mode

Demand mode

Single mode

Block mode

Cascade mode

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