PIIX3 datasheet(87/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

Connect Status Change

R/WC. 1=Change in Current Connect Status. 0=No change.

Indicates a change has occurred in the port’s Current Connect Status (see bit 0). The hub

device sets this bit for any changes to the port device connect status, even if system

software has not cleared a connect status change. If, for example, the insertion status

changes twice before system software has cleared the changed condition, hub hardware will

be “setting” an already-set bit (i.e., the bit will remain set). However, the hub transfers the

change bit only once when the Host Controller requests a data transfer to the Status Change

endpoint. System software is responsible for determining state change history in such a

case. Software sets this bit to 0 by writing a 1 to it.

Current Connect Status

RO. 1=Device is present on port. 0=No device is present. This

value reflects the current state of the port, and may not correspond directly to the event that

caused the Insertion Status Change bit (Bit 1) to be set.

Table 10 and Table 11 show Host Controller behavior when a port receives resume, connect, or disconnect

signaling and the Host Controller is in global suspend state or not in the global suspend state. A full

explanation of hub behavior is given in Chapter 11 of the USB specification. Typically, the PORTSC register

associated with the port receiving the signaling reflects the status change appropriate for the type of signaling

received. Resume signaling (K-State) is recognized in the PORTSC register only if the port is in selective

suspend (PORTSC[bits 2,12]=1,1). Resume is recognized (USBSTS[bit 2]=1), if resume is received on a

suspended or enabled port when the Host Controller is in the global suspend state (USBCMD[bit 3]=1).

The host may also initiate a resume on a suspended port or when the Host Controller has been suspended

by writing the appropriate resume-detect/force-resume bit to a 1. A global resume is started by writing

USBCMD[bit 4] to a 1. A K-State signal is sent on all enabled ports. Any port that needs to send the resume

signal and is not enabled must be enabled before the resume is forced. A resume can be forced on a

selectively suspended port by writing the corresponding PORTSC[bit 6] to a 1.

Resume signaling is ended by clearing the appropriate suspend and resume bits. This is true for either

selective or global resumes, or resumes initiated by signaling at the port or by the Host Controller. For proper

single-ended zero termination of the resume signaling, the suspend and resume bits must be simultaneously

written to 0 (same write cycle) or the suspend must be written to a 0 after the resume bit is reset. Resume is

ended on a suspended Host Controller by writing USBCMD[bits 3,4] to 0. Resume is ended on a suspended

port by writing PORTSC[bits 6,12] to 0. If signaling on a suspended port in a globally suspended Host

Controller is the source of the resume, the Host Controller suspend and resume bits should be cleared before

the port bits are cleared.

Table 10. Behavior During Resume When Host Not In Global Suspend State

Adjacent Port Response

Port Status and

Signaling Type

Signaled Port Response

Enabled Port

Disabled

Port

Suspended

Port

Port disabled,

resume K-State received

No Effect

Port suspended, Resume

K-State received

Resume reflected downstream

on signaled port. Resume

Detect status bit in PORTSC

No Effect

Port enabled, disabled or

suspended and

disconnect received

PORTSC Connect and Enable

status bits are cleared, and

Connect Change and

Enable/Disable Change status

bits are set.

No Effect

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