PIIX3 datasheet(48/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.3.3.

PCICMD—COMMAND REGISTER (Function 1)

Address Offset:

04–05h

Default Value:

0000h

Attribute:

Read/Write

The PCICMD Register controls access to the I/O space registers.

Bit

Description

15:10

Reserved. Read 0.

Fast Back to Back Enable (FBE). (Not Implemented) This bit is hardwired to 0.

8:5

Reserved. Read as 0.

Memory Write and Invalidate Enable (MWI). (Not Implemented) This bit is hardwired to 0.

Special Cycle Enable (SCE). (Not Implemented) This bit is hardwired to 0

Bus Master FunctionEnable (BME). 1=Enable. 0=Disable.

Memory Space Enable (MSE). (Not Implemented) This bit is hardwired to 1.

I/O Space Enable (IOSE). This bit controls access to the I/O space registers. When

IOSE=1, access to the Legacy IDE ports (both primary and secondary) and the PCI Bus

Master IDE I/O Registers is enabled. The Base Address Register for the PCI Bus Master IDE

I/O Registers should be programmed before this bit is set to 1.

2.3.4.

PCISTS—PCI DEVICE STATUS REGISTER (Function 1)

Address Offset:

06–07h

Default Value:

0280h

Attribute:

Read/Write

PCISTS is a 16-bit status register for the IDE interface function. The register also indicates the PIIX's

DEVSEL# signal timing.

Bit

Description

Detected Parity Error (PERR). (Not Implemented) Read as 0.

SERR# Status (SERRS). (Not Implemented) Read as 0.

Master-Abort Status (MAS)—R/W. When the Bus Master IDE interface function, as a master,

generates a master abort, MA is set to a 1. Software sets MA to 0 by writing a 1 to this bit.

Received Target-Abort Status (RTA)—R/W. When the Bus Master IDE interface function is a

master on the PCI Bus and receives a target abort, this bit is set to a 1. Software sets RTA to 0

by writing a 1 to this bit.

Signaled Target Abort Status (STA)—R/W. This bit is set when the PIIX/PIIX3 IDE interface

function is targeted with a transaction that the PIIX/PIIX3 terminates with a target abort.

Software resets STA to 0 by writing a 1 to this bit..

10:9

DEVSEL# Timing Status (DEVT)—RO. For the PIIX, DEVT=01 indicating medium timing for

DEVSEL# assertion when performing a positive decode. DEVSEL# timing does not include

configuration cycles.

PIIX3 Scheda tecnica(PDF) 48 Page - Intel Corporation

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