PIIX3 datasheet(15/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

1.5.

DMA Signals

Signal Name

Type

Description

DREQ

[7:5,3:0]

DMA REQUEST: The DREQ lines are used to request DMA service from

the PIIX/PIIX3 ’s DMA controller or for a 16-bit master to gain control of the

ISA expansion bus. The active level (high or low) is programmed via the

DMA Command Register. The request must remain active until the

appropriate DACKx# signal is asserted.

DACK

[7:5,3:0]#

DMA ACKNOWLEDGE: The DACK output lines indicate that a request

for DMA service has been granted by the PIIX/PIIX3 or that a 16-bit master

has been granted the bus. The active level (high or low) is programmed via

the DMA Command Register. These lines should be used to decode the

DMA slave device with the IOR# or IOW# line to indicate selection. If used

to signal acceptance of a bus master request, this signal indicates when it

is legal to assert MASTER#.

For the PIIX, when TC is sampled low on the assertion of PWORK

(External DMA mode), the PIIX tri-states these signals. This mode is not

available on PIIX3.

TERMINAL COUNT: The PIIX/PIIX3 asserts TC to DMA slaves as a

terminal count indicator. When all the DMA channels are not in use, TC is

negated (low).

Hardware Strapping Option (PIIX Only)

This strapping option selects between the internal ISA DMA mode and

External DMA mode. When TC is sampled high on the assertion of

PWROK (ISA DMA mode), the PIIX drives the AEN, TC, and DACK#[7:5,

3:0] normally. When TC is sampled low on the assertion of PWROK

(External DMA mode), the PIIX tri-states the AEN, TC, and DACK[7:5,

3:0]# signals, and also forwards PCI masters I/O accesses to location

0000h to ISA. TC has an internal pull-up resistor. To tie TC low, an

external 1 K

Ω pull-down resistor should be used. For the PIIX3, this signal

should not be pulled down.

REFRESH#

I/O

REFRESH: As an output, REFRESH# indicates when a refresh cycle is in

progress. It should be used to enable the SA[7:0] address to the row

address inputs of all banks of dynamic memory on the ISA Bus. Thus,

when MEMR# is asserted, the entire expansion bus dynamic memory is

refreshed. Memory slaves must not drive any data onto the bus during

refresh. As an output, this signal is driven directly onto the ISA Bus. This

signal is an output only when the PIIX/PIIX3 DMA refresh controller is a

master on the bus responding to an internally generated request for

refresh. As an input, REFRESH# is driven by 16-bit ISA Bus masters to

initiate refresh cycles.

1.6.

Timer/Counter Signals

Signal Name

Type

Description

SPKR

SPEAKER DRIVE: The SPKR signal is the output of counter 2.

OSC

OSCILLATOR: OSC is the 14.31818 MHz ISA clock signal. It is used by

the internal 8254 Timer.

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