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PIIX3 Scheda tecnica(PDF) 95 Page - Intel Corporation |
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PIIX3 Scheda tecnica(HTML) 95 Page - Intel Corporation |
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95 / 122 page  E 82371FB (PIIX) AND 82371SB (PIIX3) 95 3.5. PCI Local Bus IDE The PIIX/PIIX3 integrates a high performance interface from PCI to IDE. This interface is capable of accelerated PIO data transfers as well as acting as a PCI Bus master on behalf of an IDE DMA slave device. The PIIX/PIIX3 provides an interface for both primary and secondary IDE connectors (Figure 3). The IDE data transfer command strobes, DMA request and grant signals, and IORDY signal interface directly to the PIIX. The IDE data lines interface directly to the PIIX, and are buffered to provide part of the ISA address bus as well as the X-Bus chip select signals. The IDE address and chip select signals are multiplexed onto the LA[23:17] lines. The IDE connector signals are driven from the LA[23:17] lines by an ALS244 buffer. Only PCI masters have access to the IDE port. ISA Bus masters cannot access the IDE I/O port addresses. Memory targeted by the IDE interface acting as a PCI Bus master on behalf of IDE DMA slaves must reside on PCI, usually main memory implemented by the host-to-PCI bridge. ALS245 SOE# SDIR LA[23:17] SA[19:8] SBHE# PCS# APICCS# ISA Bus Signals ALS245 DD[15:0] Primary IDE Connector Secondary IDE Connector IORDY DIOR# DIOW# DDRQ0 DDACK0# DDRQ1 DDACK1# 051903_3.drw PIIX/PIIX3 DA[2:0] DA[2:0] CS1S# CS3S# CS1P# CS3P# SOE# 74ALS00 SOE# SDIR LA[23]/ CS1S LA[22]/ CS3S LA[21]/ CS1P LA[20]/ CS3P 051903 NOTES: Support for Older Drives: There are cases where the PIIX/PIIX3 asserts both IDE chip selects (CS1x and CS3x). Some older drives may not operate properly when both chip selects are asserted. Because the IDE chip selects are muxed with the ISA LA lines, the 74ALS00 in the figure is used to ensure proper operation of older drives by gating the LA signals with SOE#. Figure 3. PIIX/PIIX3 IDE Interface |
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