PIIX3 datasheet(9/122 Pages) INTEL

9 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

1.0.

SIGNAL DESCRIPTION

This section contains a detailed description of each signal. The signals are arranged in functional groups

according to their interface.

Note that the ’#’ symbol at the end of a signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When ’#’ is not present after the signal name, the signal is asserted when

at the high voltage level.

The terms assertion and negation are used extensively. This is done to avoid confusion when working with a

mixture of ’active-low’ and ’active-high’ signals. The term assert, or assertion indicates that a signal is active,

independent of whether that level is represented by a high or low voltage. The term negate, or negation

indicates that a signal is inactive.

Note that certain signal pins provide two separate functions. At the system level, these pins drive other

signals with different functions through external buffers or transceivers. These pins have two different signal

names depending on the function. These signal names have been noted in the signal description tables, with

the signal whose function is being described in bold font. (For example, LA23/CS1S is in the section

describing CS1S and LA23/CS1S is in the section describing LA23).

The following notations are used to describe the signal type.

Input is a standard input-only signal.

Totem Pole Output is a standard active driver.

I/O

Input/Output is a bi-directional, tri-state signal.

Open Drain allows multiple devices to share as a wire-OR.

Schmitt Trigger input.

t/s

Tri-State is a bi-directional, tri-state input/output pin.

s/t/s

Sustained Tri-state is an active low tri-state signal owned and driven by one and only one agent at a

time. The agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float.

A new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri-

states it. An external pull-up is required to sustain the inactive state until another agent drives it and

must be provided by the central resource.

1.1.

PCI Interface Signals

Signal Name

Type

Description

PCICLK

PCI CLOCK: PCICLK provides timing for all transactions on the PCI Bus.

All other PCI signals are sampled on the rising edge of PCICLK, and all

timing parameters are defined with respect to this edge. PCI frequencies of

25–33 MHz are supported.

AD[31:0]

I/O

PCI ADDRESS/DATA: The standard PCI address and data lines. The

address is driven with FRAME# assertion and data is driven or received in

following clocks

C/BE[3:0]#

I/O

BUS COMMAND AND BYTE ENABLES: The command is driven with

FRAME# assertion. Byte enables corresponding to supplied or requested

data is driven on following clocks.

FRAME#

I/O

(s/t/s)

FRAME: Assertion indicates the address phase of a PCI transfer.

Negation indicates that one more data transfer is desired by the cycle

initiator.

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