PIIX3 datasheet(52/122 Pages) INTEL

52 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

Fast Timing Bank Drive Select 1 (TIME1). When TIME1=0, accesses to the data port of

the enabled I/O address range use the 16-bit compatible timing PCI local bus path.

When TIME1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 1,

accesses to the data port of the enabled I/O address range use the fast timing bank PCI local

bus IDE path. Accesses to the data port use fast timing only if bit 7 of this register (DTE1) is

zero. Accesses to all non-data ports of the enabled I/O address range use the 8-bit

compatible timing PCI local bus path.

DMA Timing Enable Only (DTE0). When DTE0=1, fast timing mode is enabled for DMA

data transfers for drive 0. Note that PIO transfers to the IDE data port still run in compatible

timing.

Prefetch and Posting Enable (PPE0). 1=Enable; 0=Disable. When enabled, prefetch and

posting to the IDE data port is enabled for drive 0.

IORDY Sample Point Enable Drive Select 0 (IE0). When IE0=0, IORDY sampling is

disabled for Drive 0. The internal IORDY signal is forced asserted guaranteeing that IORDY

is sampled asserted at the first sample point as specified by the ISP field in this register.

When IE0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0, all

accesses to the enabled I/O address range sample IORDY. The IORDY sample point is

specified by the ISP field in this register.

Fast Timing Bank Drive Select 0 (TIME0). When TIME0=0, accesses to the data port of

the enabled I/O address range uses the 16-bit compatible timing PCI local bus path.

When TIME0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0,

accesses to the data port of the enabled I/O address range use the fast timing bank PCI local

bus IDE path. Accesses to the data port use fast timing only if bit 3 of this register (DTE0) is

0. Accesses to all non-data ports of the enabled I/O address range use the 8-bit compatible

timing PCI local bus path.

2.3.11.

SIDETIM—SLAVE IDE TIMING REGISTER (Function 1) (PIIX3 Only)

Address Offset:

44h

Default Value:

00h

Attribute:

Read / Write Only

This register controls the PIIX3’s IDE interface and selects the timing characteristics for the slave drives on

each IDE channel. This allows for programming of independent operating modes for each IDE agent. This

Bit

Description

7:6

Secondary Drive 1 IORDY Sample Point (SISP1). This field selects the number of clocks

between DIOx# assertion and the first IORDY sample point for the slave drive on the

secondary channel.

Bits[7:6]

Number Of Clocks

PIIX3 Scheda tecnica(PDF) 52 Page - Intel Corporation

PIIX3 Scheda tecnica(HTML) 52 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL