PIIX3 datasheet(45/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.21.

FTMR—FAST OFF TIMER REGISTER (Function 0)

Address Offset:

A8h

Default Value:

0Fh

Attribute:

Read/Write

The Fast Off Timer indicates (through an SMI) that the system has been idle for a pre-programmed period of

time. When the timer expires, an SMI special cycle is generated. The count time interval is programmable

(via the SMICNTL Register). The granularity of the counter is programmable via the SMICNTL Register.

NOTE

Before writing to the FTMR Register, the Fast Off Timer must be stopped via bits [4:3] of the SMICNTL

Bit

Description

7:0

Fast Off Timer Value. Bits [7:0] contain one less than the actual count-down value. Thus, if X

is programmed into this register, the countdown value is X+1. The X+1 value is loaded into the

counter when an enabled system event occurs. When the Fast Off Timer reaches 00h, an SMI

is generated and the timer is re-loaded with the X+1 value. When the Fast Off Timer is

enabled (via the SMICNTL Register), the timer counts down from this value. A read from the

FTMR Register returns the value last written.

2.2.22.

SMIREQ—SMI REQUEST REGISTER (Function 0)

Address Offset:

AA–ABh

Default Value:

00h

Attribute:

Read/Write

The SMIREQ Register contains status bits indicating which enabled event caused an SMI.

NOTE

The SMIREQ bits are set, cleared, or read independently of each other and independently of the

CSMIGATE bit in the SMICNTL Register.

If software attempts to set a status bit to 0 at the same time that the PIIX/PIIX3 is setting it to 1, the bit is

set to 1.

Each of the SMIREQ bits is set by the PIIX/PIIX3 in response to the activation of the corresponding SMI

event. If the SMI event is still active when the corresponding SMIREQ bit is set to 0, the PIIX/PIIX3 does

not set the status bit back to a 1 (i.e., there is only one status indication per active SMI event).

When an IRQx signal is asserted, the corresponding IRQx status bit is set to a 1. If the IRQx signal is still

active when software sets the corresponding status bit to 0, the status bit is not set back to a 1. The IRQx

may be negated before software sets the status bit to 0. However, If the status bit is set to 0 at the same

time a new IRQx is activated, the status bit remains at 1. This indicates to the SMI handler that a new

SMI event has been detected.

If an IRQx is set in level mode and shared by two devices, the IRQ should not be enabled as an SMI#

event. The PIIX's SMIREQ bits are essentially set with an edge. When the second IRQ occurs on a

shared IRQ, there is no second edge and the SMI# will not be generated for the second IRQ.

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