PIIX3 datasheet(43/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.18.

SMICNTL—SMI CONTROL REGISTER (Function 0)

Address Offset:

A0h

Default Value:

08h

Attribute:

Read/Write

The SMICNTL Register provides Fast Off Timer control, STPCLK# enable/disable, and CPU clock scaling.

This register also enables/disables the system management interrupt (SMI).

Bit

Description

7:5

Reserved

4:3

Fast Off Timer Freeze (CTMRFRZ). This field enables/disables the Fast Off Timer and when

enabled, selects the timer count granularity as shown below:

Bits[4:3] Count Granularity

Count Granularity

(33 MHz PCICLK)

(30 MHz PCICLK)

(25 MHz PCICLK)

1 Minute

1.1 Minute

1.32 Minute

Disabled (default)

1 PCICLK

1 Msec

1.1 Msec

1.32 Msec

STPCLK# Scaling Enable (CSTPCLKSC). 1=Enable; 0=Disable. When enabled (and bit

1=1), the high and low times for the STPCLK# signal are controlled by the Clock Scaling

STPCLK# High Timer and Clock Scaling STPCLK# Low Timer Registers.

STPCLK# Signal Enable (CSTPCLKE). 1=Enable; 0=Disable. When enabled, an APMC

disabled and is negated (high). Software can set this bit to 0 by writing a 0 to it.

SMI# Gate (CSMIGATE). 1=Enable; 0=Disable. When enabled, a system management

interrupt condition asserts the SMI# signal. When disabled, the SMI# signal is masked and

negated. This bit only affects the SMI# signal and does not affect the detection/recording of

SMI events (i.e., This bit does not effect the SMI status bits in the SMIREQ Register). Thus, if

an SMI is pending when this bit is set to 1, the SMI# signal is asserted.

2.2.19.

SMIEN—SMI ENABLE REGISTER (Function 0)

Address Offset:

−A3h

Default Value:

0000h

Attribute:

Read/Write

This register enables the generation of SMI (asserting the SMI# signal) for the associated hardware events

(bits [5:0]), and software events (bit 7). When a hardware event is enabled, the occurrence of a

corresponding event results in the assertion of SMI#, if enabled via the SMICNTL Register. The SMI# is

asserted independent of the current power state (Power-On or Fast Off). The default for all sources in this

Bit

Description

15:9

Reserved.

PIIX: Reserved.

PIIX3: Legacy USB SMI Enable 1=Enable USB Legacy logic to generate SMI#. 0=Disable

(default).

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