PIIX3 datasheet(57/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.4.8.

HEDT

HEADER TYPE REGISTER (Function 2) (PIIX3)

Address Offset:

0Eh

Default Value:

00h

Attribute:

Read Only

This register identifies the Serial Bus module as a single function device.

Bit

Description

7:0

Device Type (DEVICET). 00. Multi-function device capability for PIIX/PIIX3 is defined by the

HEDT register in Function 0.

2.4.9.

BASEADD

I/O SPACE BASE ADDRESS (Function 2) (PIIX3)

Address Offset:

−23h

Default Value:

00h

Attribute:

Read/Write

This register contains the base address of the USB I/O Registers.

Bit

Description

31:16

Reserved. Hardwired to 0s. Must be written as 0s.

15:5

Index Register Base Address. Bits [15:5] correspond to I/O address signals AD [15:5],

respectively.

4:1

Reserved. Read as 0.

Resource Type Indicator (RTE)—RO. This bit is hardwired to 1 indicating that the base

address field in this register maps to I/O space.

2.4.10.

Interrupt Line Register (Function 2) (PIIX3)

Address Offset:

3Ch

Default Value:

00h

Attribute:

Read/Write

Software programs this register with interrupt information concerning the Universal Serial Bus.

Bit

Description

7:0

Interrupt Line. . The value in this register has no affect on PIIX3 hardware operations.

PIIX3 Scheda tecnica(PDF) 57 Page - Intel Corporation

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