PIIX3 datasheet(100/122 Pages) INTEL

100 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

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Note that the IRQ14 signal must be used to signal interrupts for the primary channel in bus master mode;

MIRQ0 must be used for the secondary channel.

When the last data transfer for a region has been completed on the IDE interface, the next descriptor is

fetched from the table. The descriptor contents are loaded into the Current Base and Current Count registers.

The last PRD in a table has the End of List (EOL) bit set. The PCI Bus master data transfers terminates when

the physical region described by the last PRD in the table has been completely transferred. The active bit in

the BMISx Register is set to 0 and the DDRQx signal is masked.

Line Buffer

A single line buffer exists for the PCI Bus master IDE interface. This buffer is not shared with any other

function. The buffer is maintained in either the read state or the write state. Writes are always 4-DWord bursts

and invalid DWords have C/BE[3:0]#=F. The size of the buffer is 32 bytes, and is aligned on the cache line

boundary. The line buffer allows burst data transfers to proceed at peak transfer rates.

3.6.

Universal Serial Bus Host Controller (PIIX3 only)

PIIX3 contains a USB Host Controller (HC). The Host Controller includes the root hub with two USB ports.

This permits connection of two USB peripheral devices directly to the PIIX3 without an external hub. If more

devices are required, an external hub can be connected to either of the built-in ports. The USB’s PCI

configuration registers are located in function 2, PCI configuration space. The PIIX3 Host Controller

completely supports the standard Universal Host Controller Interface (UHCI) and thus, takes advantage of the

standard software drivers written to be compatible with UHCI. Figure 6 Shows a conceptual view of a USB

system. UHCI consists of two parts

 Host Controller Driver (HCD) and Host Controller (HC). The Host

Controller interfaces to the USB system software in the host via the HCD. The HCD software manages the

Host Controller operation and is responsible for scheduling the traffic on USB by posting and maintaining

transactions in system memory. HCD is part of the system software and is typically provided by the operating

system vendor. HCD provides the software layer between the PIIX3’s Host Controller and the USBD software

layer (also located in the operating system). The UHCI’s HCD software interprets requests from the USBD

and builds Frame List, Transfer Descriptor, Queue Head, and data buffer data structures for the Host

Controller. The data structures are built in system memory and contain all necessary information to provide

end-to-end communication between client software in the host and devices on the USB.

The PIIX3’s Host Controller moves data between system memory and devices on the USB by processing

these data structures and generating the transaction on USB. The Host Controller executes the schedule lists

generated by HCD and reports the status of transactions on the USB to HCD. Command execution includes

generating serial bus token and/or data packets based on the command and initiating transmission on USB.

For commands that require the Host Controller to receive data from the USB device, the Host Controller

receives the data and then transfers it to the system memory pointed to by the command. The UHCI’s HCD

provides sufficient commands and data to keep ahead of the Host Controller execution and analyzes the

results as the commands are completed.

The PIIX3 provides support for USB Keyboard and Mouse operation with an operating system environment

which does not have the complete USB software drivers loaded. This allows application programs which

directly access system I/O space to function with a USB keyboard or mouse. The USB system will emulate a

8042 based keyboard controller.

The PIIX3 has five controller issues regarding USB transactions, each of which is described below.

Multiple USB Babble Interrupts may be observed. If a babble occurs in a frame, a hardware interrupt will be

generated at the end of the frame. Additionally, the interrupt will occur in empty frames which immediately

follow the frame in which the babble occurred and also in the first non-empty frame. An empty frame is

defined as one with no active transfer descriptors (TDs). This means extra hardware interrupts can be

generated to the system. These interrupts are treated as spurious interrupts by the HCD interrupt handler.

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