PIIX3 datasheet(33/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.5.

RID—REVISION IDENTIFICATION REGISTER (Function 0)

Address Offset:

08h

Default Value:

Refer to applicable specification update document

Attribute:

Read Only

This 8 bit register contains device stepping information. Writes to this register have no effect.

Bit

Description

7:0

Revision ID Byte. The register is hardwired to the default value.

2.2.6.

CLASSC

CLASS CODE REGISTER (Function 0)

Address Offset:

−0Bh

Default Value:

060100h

Attribute:

Read Only

This register contains the device programming interface information related to the Sub-Class Code and Base

Class Code definition for the PIIX3 (function 0). This register also identifies the Base Class Code and the

function sub-class in relation to the Base Class Code.

Bit

Description

23:1

Base Class Code (BASEC). 06h=Bridge device.

15:8

Sub-Class Code (SCC). 01h=PCI-to-ISA Bridge.

7:0

Programming Interface (PI). 00h=hardwired as a PCI-to-ISA Bridge.

2.2.7.

HEDT—HEADER TYPE REGISTER (Function 0)

Address Offset:

0Eh

Default Value:

80h

Attribute:

Read Only

The HEDT Register identifies the PIIX/PIIX3 as a multi-function device.

Bit

Description

7:0

Device Type (DEVICET). 80h=multi-function device.

2.2.8.

IORT—ISA I/O RECOVERY TIMER REGISTER (Function 0)

Address Offset:

4Ch

Default Value:

4Dh

Attribute:

Read/Write

The I/O recovery mechanism in the PIIX/PIIX3 is used to add additional recovery delay between CPU or PCI

master originated 8-bit and 16-bit I/O cycles to the ISA Bus. The PIIX/PIIX3 automatically forces a minimum

delay of 3.5 SYSCLKs between back-to-back 8 and 16-bit I/O cycles to the ISA Bus. This delay is measured

from the rising edge of the I/O command (IOR# or IOW#) to the falling edge of the next I/O command. If a

delay of greater than 3.5 SYSCLKs is required, the ISA I/O Recovery Time Register can be programmed to

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