PIIX3 datasheet(84/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

select a particular entry in the Frame List during schedule execution. (Frame List is one of the data structures

located in system memory that is processed by the Host Controller.)

This register must be written as a word. Byte writes are not supported. This register cannot be written unless

the Host Controller is in the STOPPED state as indicated by the HCHalted bit (USBSTS register). A write to

this register while the Run/Stop bit (USBCMD register) is set is ignored.

Bit

Description

15:11

Reserved.

10:0

Frame List Current Index/Frame Number. Bits [10:0] provide the frame number in the SOF

Frame. The value in this register increments at the end of each time frame (approximately

every 1 ms). In addition, bits [9:0] are used for the Frame List current index and correspond

to memory address signals [11:2].

2.8.5.

FLBASEADD

Frame List Base Address Register

I/O Address:

Base + (08

−0Bh)

Default Value:

Undefined

Attribute:

Read/Write

Size:

32 bits

This 32-bit register contains the beginning address of the Frame List in the system memory. Software loads

this register prior to starting the schedule execution by the Host Controller. When written, only the upper 20

bits are used. The lower 12 bits are written as zero (4 Kbyte alignment). The contents of this register are

combined with the frame number counter to enable the Host Controller to step through the Frame List in

sequence. The two lsb are always 00. This requires DWord alignment for all list entries. This configuration

supports 1K (1024) Frame List entries.

Note that Frame List is one of the data structures located in system memory that is processed by the Host

Controller during schedule execution.

Bit

Description

31:12

Base Address. These bits correspond to memory address signals [31:12], respectively.

11:0

Reserved. Must be written as 0s.

2.8.6.

Start Of Frame (SOF) Modify Register

I/O Address:

Base + (0Ch)

Default Value:

Attribute:

Read/Write

Size:

8 bits

This one byte register is used to modify the value used in the generation of SOF timing on the USB. Only the

7 least significant bits are used. When a new value is written into the these 7 bits, the SOF timing of the next

frame will be adjusted. This feature can be used to adjust out any offset from the frequency synthesizer that

generates the clock that drives the SOF counter. This register can also be used to maintain real time

synchronization with the rest of the system so that all devices have the same sense of real time. Using this

It’s initial programmed value is system dependent based on the accuracy of hardware USB clock and is

initialized by system BIOS. It may be reprogrammed by USB system software at any time. Its new value will

PIIX3 Scheda tecnica(PDF) 84 Page - Intel Corporation

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