PIIX3 datasheet(96/122 Pages) INTEL

96 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

Two connectors (primary and secondary) and two drives per connector (master and slave) are supported as

shown in Figure 4.

PIIX/PIIX3

ideconn.drw

Master

(Drive 0)

Slave

(Drive 1)

Primary

Connector (P)

Master

(Drive 0)

Slave

(Drive 1)

Secondary

Connector (S)

IDECONN

Figure 4. IDE Connector and Drive Nomenclature

3.5.1.

ATA REGISTER BLOCK DECODE

The IDE ATA I/O ports are decoded by the PIIX/PIIX3 when enabled in the PCICMD and IDETIM Registers

for function 1. (ATA stands for "AT Attachment"—the specification for AT compatible drive interfaces). The

actual ATA registers are implemented in the drive itself. An access to the IDE registers results in the

assertion of the appropriate chip select for the register. The transaction is then run using compatible timing

and using the IDE command strobes (DIOR#, DIOW#).

For each cable (primary and secondary), there are two I/O ranges; the Command block that corresponds to

the CS1x# chip select, and the control block that corresponds to the CS3x# chip select. The command block

is an 8 byte range while the control block is a 4 byte range. The upper 16 bits of the I/O address are decoded

as all 0s.

Primary Command Block Offset:

01F0h

Primary Control Block Offset:

03F4h

Secondary Command Block Offset:

0170h

Secondary Control Block Offset:

0374h

Table 13 specifies the registers as they affect the PIIX/PIIX3 hardware definition.

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