PIIX3 datasheet(89/122 Pages) INTEL

89 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

3.0.

FUNCTIONAL DESCRIPTION

This section describes each of the major functions on the PIIX/PIIX3 including the memory and I/O address

map, DMA controller, interrupt controller, timer/counter, and power management. The PCI, ISA, X-Bus, and

IDE interfaces.

3.1.

Memory and I/O Address Map

The PIIX/PIIX3 interfaces to two system buses—PCI and ISA Buses. The PIIX/PIIX3 provides positive

decode for certain I/O and memory space accesses on these buses as described in this section.

ISA masters and DMA devices have access to PCI memory and some of the internal PIIX/PIIX3 registers as

described in the Register Description section. ISA masters and DMA devices do not have access to host or

PCI I/O space.

3.1.1.

I/O Accesses

The PIIX/PIIX3 positively decodes accesses to the PCI configuration registers (PCI only), power

management registers (PCI only), and bus master IDE interface registers (PCI only). The PIIX/PIIX3

subtractively decodes memory accesses to the APIC Registers (PCI only), The PIIX/PIIX3 also positively

decodes the ISA-Compatible registers (PCI and ISA), except for the DMA register I/O space which is

subtractively decoded. For details concerning accessing these registers, see Register Description section.

The PIIX/PIIX3 also provides positive decode for BIOS, X-Bus, and system event decode for SMM support.

In addition, the PIIX/PIIX3 positively decodes PCI Bus accesses to registers located on the IDE device, when

enabled. For IDE port accesses, see PCI Local Bus IDE section.

3.1.2.

Memory Address Map

For PCI accesses to ISA memory, accesses below 16 Mbytes (including BIOS space) that are not claimed by

a PCI device (subtractive decode) are forwarded to ISA. For write accesses that are not claimed by an ISA

slave, the cycle completes normally (i.e., 8-bit, 6 SYSCLK cycle). For read accesses that are not claimed by

an ISA slave, the PIIX/PIIX3 returns data corresponding to the state of the ISA Bus and completes the cycle

normally (i.e., 8-bit, 6 SYSCLK cycle).

For ISA/DMA accesses to main memory, all accesses to memory locations 0–512 Kbytes (512–640 Kbytes, if

enabled), or accesses above 1 Mbyte and below the top of memory are forwarded to the PCI Bus (Table 12).

The Top of Memory is equal to the value programmed in the Top of Memory Register (bits [7:3]). The PIIX3

can also enable ISA/DMA accesses to the VGA frame buffer space from 640-768 Kbytes (A0000-BFFFFh).

All remaining ISA originated accesses are confined to the ISA Bus.

Table 12. DMA and ISA Master Accesses to Main Memory

Memory Space

Response

Top of main memory to 128 Mbytes

Confine to ISA

1 Mbyte to top of main memory

Forward to main memory1

1 Mbyte minus 128 Kbytes to 1 Mbyte minus 64 Kbytes

Confine to ISA2

640 Kbytes to 1 Mbyte minus 128 Kbytes

Confine to ISA

512–640 Kbytes

Confine to ISA3

0–512 Kbytes

Forward to PCI

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