HYB18T512400B2C datasheet(38/69 Pages) QIMONDA

38 / 69 page

Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

Currents Measurement Conditions

This chapter describes the Current Measurement, Specifications and Conditions.

TABLE 38

DD Measurement Conditions

Parameter

Symbol Note

Operating Current - One bank Active - Precharge

CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address

and control inputs are switching; Databus inputs are switching.

DD0

1)2)3)4)5)

Operating Current - One bank Active - Read - Precharge

OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);

CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus

inputs are switching.

DD1

1)2)3)4)5)

Precharge Power-Down Current

All banks idle; CKE is LOW;

CK = tCK(IDD); Other control and address inputs are stable; Data bus inputs are

floating.

DD2P

1)2)3)4)5)

Precharge Standby Current

All banks idle; CS is HIGH; CKE is HIGH;

CK = tCK(IDD); Other control and address inputs are switching,

Data bus inputs are switching.

DD2N

1)2)3)4)5)

Precharge Quiet Standby Current

All banks idle; CS is HIGH; CKE is HIGH;

CK = tCK(IDD); Other control and address inputs are stable, Data

bus inputs are floating.

DD2Q

1)2)3)4)5)

Active Power-Down Current

All banks open;

CK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs

are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).

DD3P(0)

1)2)3)4)5)

Active Power-Down Current

All banks open;

CK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs

are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);

DD3P(1)

1)2)3)4)5)

Active Standby Current

All banks open;

CK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid

commands. Address inputs are switching; Data Bus inputs are switching;

DD3N

1)2)3)4)5)

Operating Current

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =

RAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are

switching; Data Bus inputs are switching;

OUT = 0 mA.

DD4R

1)2)3)4)5)

Operating Current

Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =

RAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are

switching; Data Bus inputs are switching;

DD4W

1)2)3)4)5)

Burst Refresh Current

CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are switching, Data bus inputs are switching.

DD5B

1)2)3)4)5)

Distributed Refresh Current

CK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH between valid

commands, Other control and address inputs are switching, Data bus inputs are switching.

DD5D

1)2)3)4)5)

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