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HYB18T512400B2C Scheda tecnica(PDF) 39 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 39 Page - Qimonda AG |
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39 / 69 page ![]() Internet Data Sheet Rev. 1.12, 2007-05 39 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM TABLE 39 Definition for I DD Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. I DD6 1)2)3)4)5) 6) Operating Bank Interleave Read Current 1. All banks interleaving reads, I OUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD), t RC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 2. Timing pattern: I DD7 1)2)3)4)5) 6)7) DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks) DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks) DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks) DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks) DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks) DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks) 1) V DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) I DD specifications are tested after the device is properly initialized. 3) I DD parameter are specified with ODT disabled. 4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. 5) Definitions for I DD: see Table 39 6) Timing parameter minimum and maximum values for I DD current measurements are defined in Chapter 7. 7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT Parameter Description LOW defined as V IN ≤ VIL(ac).MAX HIGH defined as V IN ≥ VIH(ac).MIN STABLE defined as inputs are stable at a HIGH or LOW level FLOATING defined as inputs are V REF = VDDQ / 2 SWITCHING defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes Parameter Symbol Note |
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