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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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HYB18T512400B2C Scheda tecnica(PDF) 55 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 55 Page - Qimonda AG |
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55 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 55 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Clock half period t HP MIN. ( t CL, tCH) 11) Data-out high-impedance time from CK / CK t HZ — t AC.MAX ps 12) Address and control input hold time t IH(base) 475 — ps 10) Address and control input pulse width (each input) t IPW 0.6 — t CK Address and control input setup time t IS(base) 350 — ps 10) DQ low-impedance time from CK / CK t LZ(DQ) 2 × t AC.MIN t AC.MAX ps 13) DQS low-impedance from CK / CK t LZ(DQS) t AC.MIN t AC.MAX ps 13) Mode register set command cycle time t MRD 2— t CK OCD drive mode output delay t OIT 012 ns Data output hold time from DQS t QH t HP –tQHS — Data hold skew factor t QHS — 450 ps Average periodic refresh Interval t REFI —7.8 µs 13)14) Average periodic refresh Interval t REFI —3.9 µs 15)17) Auto-Refresh to Active/Auto-Refresh command period 105 — ns 16) Precharge-All (4 banks) command period t RP t RP —ns Read preamble t RPRE 0.9 1.1 t CK 13) Read postamble t RPST 0.40 0.60 t CK 13) Active bank A to Active bank B command period t RRD 7.5 — ns 13)17) Active bank A to Active bank B command period t RRD 10 — ns 15)21) Internal Read to Precharge command delay t RTP 7.5 — ns Write preamble t WPRE 0.25 — t CK Write postamble t WPST 0.40 0.60 t CK 18) Write recovery time for write without Auto- Precharge t WR 15 — ns Internal Write to Read command delay t WTR 10 — ns 19) Exit power down to any valid command (other than NOP or Deselect) t XARD 2— t CK 20) Exit active power-down mode to Read command (slow exit, lower power) t XARDS 6 – AL — t CK 20) Exit precharge power-down to any valid command (other than NOP or Deselect) t XP 2— t CK Exit Self-Refresh to non-Read command t XSNR t RFC +10 — ns Exit Self-Refresh to Read command t XSRD 200 — t CK Write recovery time for write with Auto- Precharge WR t WR/tCK — t CK 21) 1) V DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6) Min. Max. |
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