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Motore di ricerca datesheet componenti elettronici |
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HYB18T512400B2C Scheda tecnica(PDF) 54 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 54 Page - Qimonda AG |
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54 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 54 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM TABLE 48 DRAM Component Timing Parameter by Speed Grade - DDR2-400 13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 14) 0 °C ≤ T CASE ≤ 85 °C 15) 85 °C < T CASE ≤ 95 °C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The t RRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for Lead-Free Products (RoHS Compliant)” on Page 6. 18) The maximum limit for the t WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum t WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power- down mode” (MR, A12 = “0”) a fast power-down exit timing t XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing t XARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the t WR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. t DAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6) Min. Max. DQ output access time from CK / CK t AC –600 +600 ps CAS A to CAS B command period t CCD 2— t CK CK, CK high-level width t CH 0.45 0.55 t CK CKE minimum high and low pulse width t CKE 3— t CK CK, CK low-level width t CL 0.45 0.55 t CK Auto-Precharge write recovery + precharge time t DAL WR + t RP — t CK 7)20) Minimum time clocks remain ON after CKE asynchronously drops LOW t DELAY t IS + tCK + tIH –– ns 8) DQ and DM input hold time (differential data strobe) t DH(base) 275 –– ps 9) DQ and DM input hold time (single ended data strobe) t DH1(base) –25 — ps 10) DQ and DM input pulse width (each input) t DIPW 0.35 — t CK DQS output access time from CK / CK t DQSCK –500 +500 ps DQS input low (high) pulse width (write cycle) t DQSL,H 0.35 — t CK DQS-DQ skew (for DQS & associated DQ signals) t DQSQ — 350 ps 10) Write command to 1st DQS latching transition t DQSS – 0.25 + 0.25 t CK DQ and DM input setup time (differential data strobe) t DS(base) 150 — ps 10) DQ and DM input setup time (single ended data strobe) t DS1(base) –25 — ps 10) DQS falling edge hold time from CK (write cycle) t DSH 0.2 — t CK DQS falling edge to CK setup time (write cycle) t DSS 0.2 — t CK |
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