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HYB18T512400B2C Scheda tecnica(PDF) 48 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 48 Page - Qimonda AG |
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48 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 48 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Mode register set command cycle time t MRD 2— nCK OCD drive mode output delay t OIT 012 ns 34) DQ/DQS output hold time from DQS t QH t HP – tQHS —ps 25) DQ hold skew factor t QHS — 340 ps 26) Average periodic refresh Interval t REFI —7.8 µs 27)28) —3.9 µs 28)29) Auto-Refresh to Active/Auto-Refresh command period t RFC 105 — ns 30) Precharge-All (4 banks) command period t RP t RP —ns Read preamble t RPRE 0.9 1.1 t CK.AVG 31)32) Read postamble t RPST 0.4 0.6 t CK.AVG 31)33) Internal Read to Precharge command delay t RTP 7.5 — ns 34) Write preamble t WPRE 0.35 — t CK.AVG Write postamble t WPST 0.4 0.6 t CK.AVG Write recovery time t WR 15 — ns 34) Internal write to read command delay t WTR 7.5 — ns 34)35) Exit power down to read command t XARD 2— nCK Exit active power-down mode to read command (slow exit, lower power) t XARDS 7 – AL — nCK Exit precharge power-down to any valid command (other than NOP or Deselect) t XP 2— nCK Exit self-refresh to a non-read command t XSNR t RFC +10 — ns 34) Exit self-refresh to read command t XSRD 200 — nCK Write command to DQS associated clock edges WL RL–1 nCK 1) V DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS, RDQS / RDQS is defined. 5) Inputs are not recognized as valid until V REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is V TT. 7) New units, ‘ t CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘ t CK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t CK.AVG + tERR.2PER(Min). 8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t ERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t ERR(6-10PER).MIN = – 272 ps and t ERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and t DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and t LZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) Min. Max. |
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