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HYB18T512400B2C Scheda tecnica(PDF) 60 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 60 Page - Qimonda AG |
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60 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 60 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM 7.4 ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. TABLE 52 ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 TABLE 53 ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800 Symbol Parameter / Condition Values Unit Note Min. Max. t AOND ODT turn-on delay 2 2 t CK t AON ODT turn-on t AC.MIN t AC.MAX + 1 ns ns 1) 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from t AOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if t CK = 5 ns. t AONPD ODT turn-on (Power-Down Modes) t AC.MIN + 2 ns 2 t CK + tAC.MAX + 1 ns ns t AOFD ODT turn-off delay 2.5 2.5 t CK t AOF ODT turn-off t AC.MIN t AC.MAX + 0.6 ns ns 2) 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from t AOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if t CK = 5 ns. t AOFPD ODT turn-off (Power-Down Modes) t AC.MIN + 2 ns 2.5 t CK + tAC.MAX + 1 ns ns t ANPD ODT to Power Down Mode Entry Latency 3 — t CK t AXPD ODT Power Down Exit Latency 8 — t CK Symbol Parameter / Condition Values Unit Note Min. Max. t AOND ODT turn-on delay 2 2 n CK 1) 1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock under operation. Unit “ n CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, “ t CK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at T m + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). t AON ODT turn-on t AC.MIN t AC.MAX + 0.7 ns ns 1)2) 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from t AOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. t AONPD ODT turn-on (Power-Down Modes) t AC.MIN + 2 ns 2 t CK + tAC.MAX + 1 ns ns 1) t AOFD ODT turn-off delay 2.5 2.5 n CK 1) t AOF ODT turn-off t AC.MIN t AC.MAX + 0.6 ns ns 1)3) 3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from t AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. t AOFPD ODT turn-off (Power-Down Modes) t AC.MIN + 2 ns 2.5 t CK + tAC.MAX + 1 ns ns 1) t ANPD ODT to Power Down Mode Entry Latency 3 — n CK 1) t AXPD ODT Power Down Exit Latency 8 — n CK 1) |
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