HYB18T512400B2C datasheet(20/69 Pages) QIMONDA

20 / 69 page

Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

TABLE 12

Extended Mode Register Definition (BA[2:0] = 001B)

[6:4]

CAS Latency

Note: All other bit combinations are illegal.

011B CL 3

100B CL 4

101B CL 5

110B CL 6

111B CL 7

Burst Type

BT Sequential

BT Interleaved

[2:0]

Burst Length

Note: All other bit combinations are illegal.

010B BL 4

011B BL 8

1) w = write only register bits

2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing

WR (in ns) by tCK (in ns) and

rounding up to the next integer: WR [cycles]

≥ t

WR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement

for the analogue

WR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.

Field

Bits

Type1)

Description

BA2

reg. addr.

Bank Address [2]

Note: BA2 not available on 256 Mbit and 512 Mbit components

BA2 Bank Address

BA1

Bank Address [1]

BA1 Bank Address

BA0

Bank Address [0]

BA0 Bank Address

A13

Address Bus [13]

Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration

A13 Address bit 13

Qoff

Output Disable

QOff Output buffers enabled

QOff Output buffers disabled

Field

Bits

Type1)

Description

HYB18T512400B2C Scheda tecnica(PDF) 20 Page - Qimonda AG

HYB18T512400B2C Scheda tecnica(HTML) 20 Page - Qimonda AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Scheda tecnica Scarica

Link URL