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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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HYB18T512400B2C Scheda tecnica(PDF) 44 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 44 Page - Qimonda AG |
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44 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 44 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM 7.2 Component AC Timing Parameters List of Timing Parameters Tables. TABLE 45 DRAM Component Timing Parameter by Speed Grade - DDR2–800 Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) Min. Max. DQ output access time from CK / CK t AC –400 +400 ps 8) CAS to CAS command delay t CCD 2— nCK Average clock high pulse width t CH.AVG 0.48 0.52 t CK.AVG 9)10) Average clock period t CK.AVG 2500 8000 ps 9)10) CKE minimum pulse width ( high and low pulse width) t CKE 3— nCK 11) Average clock low pulse width t CL.AVG 0.48 0.52 t CK.AVG 9)10) Auto-Precharge write recovery + precharge time t DAL WR + t nRP —nCK 12)13) Minimum time clocks remain ON after CKE asynchronously drops LOW t DELAY t IS + tCK .AVG + t IH –– ns DQ and DM input hold time t DH.BASE 125 –– ps 18)19)14) DQ and DM input pulse width for each input t DIPW 0.35 — t CK.AVG DQS output access time from CK / CK t DQSCK –350 +350 ps 8) DQS input high pulse width t DQSH 0.35 — t CK.AVG DQS input low pulse width t DQSL 0.35 — t CK.AVG DQS-DQ skew for DQS & associated DQ signals t DQSQ — 200 ps 15) DQS latching rising transition to associated clock edges t DQSS – 0.25 + 0.25 t CK.AVG 16) DQ and DM input setup time t DS.BASE 50 –– ps 17)18)19) DQS falling edge hold time from CK t DSH 0.2 — t CK.AVG 16) DQS falling edge to CK setup time t DSS 0.2 — t CK.AVG 16) CK half pulse width t HP Min( t CH.ABS, t CL.ABS) __ ps 20) Data-out high-impedance time from CK / CK t HZ — t AC.MAX ps 8)21) Address and control input hold time t IH.BASE 250 — ps 22)24) Control & address input pulse width for each input t IPW 0.6 — t CK.AVG Address and control input setup time t IS.BASE 175 — ps 23)24) DQ low impedance time from CK/CK t LZ.DQ 2x t AC.MIN tAC.MAX ps 8)21) DQS/DQS low-impedance time from CK / CK t LZ.DQS t AC.MIN t AC.MAX ps 8)21) MRS command to ODT update delay t MOD 012 ns 34) Mode register set command cycle time t MRD 2— nCK OCD drive mode output delay t OIT 012 ns 34) DQ/DQS output hold time from DQS t QH t HP – tQHS —ps 25) DQ hold skew factor t QHS — 300 ps 26) |
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