HYB18T512400B2C datasheet(23/69 Pages) QIMONDA

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Internet Data Sheet

Rev. 1.12, 2007-05

10062006-YPTZ-CDR7

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

TABLE 14

EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B)

Partial Self Refresh for 8 banks

PASR [2:0]

Address Bus, Partial Array Self Refresh for 8 Banks3)

Note: Only for 1G and 2G components

000B PASR0 Full Array

001B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)

010B PASR2 Quarter Array (BA[2:0]=000, 001)

011B PASR3 1/8 array (BA[2:0] = 000)

100B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)

101B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)

110B PASR6 Quarter array (BA[2:0]= 110 & 111)

111B PASR7 1/8 array(BA[2:0]=111)

1) w = write only

2) When DRAM is operated at 85

°C ≤ T

Case £ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self

refresh mode can be entered.

3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh

is entered. Data integrity will be maintained if

REF conditions are met and no Self Refresh command is issued

Field

Bits

Type1)

1) w = write only

Description

BA2

reg.addr

Bank Address[2]

Note: BA2 is not available on 256Mbit and 512Mbit components

BA2 Bank Address

BA1

Bank Adress[1]

BA1 Bank Address

BA0

Bank Adress[0]

BA0 Bank Address

[13:0] w

Address Bus[13:0]

Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration

00000000000000BA[13:0] Address bits

Field

Bits

Type1)

Description

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