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HYB18T512400B2C Scheda tecnica(PDF) 31 Page - Qimonda AG |
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HYB18T512400B2C Scheda tecnica(HTML) 31 Page - Qimonda AG |
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31 / 69 page ![]() Internet Data Sheet Rev. 1.12, 2007-05 31 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM TABLE 27 Single-ended AC Input Test Conditions FIGURE 4 Single-ended AC Input Test Conditions Diagram Symbol Condition Value Unit Note V REF Input reference voltage 0.5 x V DDQ V 1) 1) Input waveform timing is referenced to the input signal crossing through the V REF level applied to the device under test. V SWING.MAX Input signal maximum peak to peak swing 1.0 V 1) SLEW Input signal minimum Slew Rate 1.0 V / ns 2)3) 2) The input signal minimum Slew Rate is to be maintained over the range from V IH(ac).MIN to VREF for rising edges and the range from VREF to V IL(ac).MAX for falling edges as shown in Figure 4 3) AC timings are referenced with input waveforms switching from V IL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. |
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